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1. 发明申请

US20230139263A1 LOGIC DRIVE BASED ON STANDARDIZED COMMODITY PROGRAMMABLE LOGIC SEMICONDUCTOR IC CHIPS 有权
公开(公告)号：US20230139263A1
公开(公告)日：2023-05-04
申请号：US17994466
申请日：2022-11-28
申请人： iCometrue Company Ltd.
发明人： Jin-Yuan Lee , Mou-Shiung Lin
IPC分类号： H01L25/18 , H03K19/17736 , H03K19/17796 , H01L23/522 , H01L23/498 , H01L23/00 , H01L23/528 , H01L23/31 , H01L21/56
摘要： A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.

2. 发明授权

US11600526B2 Chip package based on through-silicon-via connector and silicon interconnection bridge 有权
公开(公告)号：US11600526B2
公开(公告)日：2023-03-07
申请号：US17155069
申请日：2021-01-21
申请人： iCometrue Company Ltd.
发明人： Jin-Yuan Lee , Mou-Shiung Lin
IPC分类号： H01L21/768 , H01L21/78 , H01L21/48
摘要： A method for a through-silicon-via (TSV) connector includes: providing a semiconductor wafer with a silicon substrate, wherein the semiconductor wafer has a frontside and a backside opposite to the frontside thereof; forming multiple holes in the silicon substrate of the semiconductor wafer; forming a first insulating layer at a sidewall and bottom of each of the holes; forming a metal layer over the semiconductor wafer and in each of the holes; polishing the metal layer outside each of the holes to expose a frontside surface of the metal layer in each of the holes; forming multiple metal bumps or pads each on the frontside surface of the metal layer in at least one of the holes; grinding a backside of the silicon substrate of the semiconductor wafer to expose a backside surface of the metal layer in each of the holes, wherein the backside surface of the metal layer in each of the holes and a backside surface of the silicon substrate of the semiconductor wafer are coplanar; and cutting the semiconductor wafer to form multiple through-silicon-via (TSV) connectors.

3. 发明授权

US11232562B2 Method for data management and machine learning with fine resolution 有权
公开(公告)号：US11232562B2
公开(公告)日：2022-01-25
申请号：US17073353
申请日：2020-10-18
申请人： iCometrue Company Ltd.
发明人： Jin-Yuan Lee , Mou-Shiung Lin
IPC分类号： G06K9/00 , G06T7/00 , G16H30/40 , A61B5/055 , A61B6/03 , A61B8/08 , A61B10/00 , G06N20/00
摘要： A method for obtaining a probability in a 3D probability map, includes: obtaining at least one value of at least one parameter for each stop of a 3D moving window, wherein a first, second, third and fourth of the stops are partially overlapped, the first and second stops are shifted from each other by a distance equal to a first dimension of a computation voxel, the first and third stops are shifted from each other by a distance equal to a second dimension of the computation voxel, and the first and fourth stops are shifted from each other by a distance equal to a third dimension of the computation voxel; matching the at least one value to a classifier to obtain a first probability for each stop of the 3D moving window; and calculating a second probability for the computation voxel based on information associated with the first probabilities for the first through fourth stops.

4. 发明申请

US20210143124A1 LOGIC DRIVE BASED ON MULTICHIP PACKAGE USING INTERCONNECTION BRIDGE 有权
公开(公告)号：US20210143124A1
公开(公告)日：2021-05-13
申请号：US17151634
申请日：2021-01-18
申请人： iCometrue Company Ltd.
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L23/00 , H01L23/522 , H03K19/17736 , H03K19/1776 , H03K19/17728 , H01L23/532 , H03K19/17704 , H01L23/538 , H01L25/065
摘要： A multi-chip package comprising: an interconnection substrate comprising an interconnection bridge embedded in the interconnection substrate, and an interconnection scheme comprising a first interconnection metal layer, a second interconnection metal layer over the first interconnection layer and the interconnection bridge, and a polymer layer between the first and second interconnection metal layers, wherein the interconnection bridge is embedded in the interconnection scheme and has sidewalls surrounded by the polymer layer; a semiconductor IC chip over the interconnection substrate and across over an edge of the interconnection bridge; a memory chip over the interconnection substrate and across over an edge of the interconnection bridge, wherein the interconnection bridge comprises a plurality of metal interconnects configured for a data bus coupling the semiconductor IC chip to the memory chip, wherein a bitwidth of the data bus between the semiconductor IC chip and the memory chip is greater than or equal to 512.

5. 发明申请

US20210090983A1 3D CHIP PACKAGE BASED ON THROUGH-SILICON-VIA INTERCONNECTION ELEVATOR 有权
公开(公告)号：US20210090983A1
公开(公告)日：2021-03-25
申请号：US17026186
申请日：2020-09-19
申请人： iCometrue Company Ltd.
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： H01L23/498
摘要： A chip package includes a first interconnection scheme; a plurality of first metal contacts under and on the first interconnection scheme and at a bottom surface of the chip package; a first semiconductor IC chip over the first interconnection scheme; a first connector over the first interconnection scheme and at a same horizontal level as the first semiconductor IC chip, wherein the first connector comprises a first substrate and a plurality of first through vias vertically extending through the first substrate of the first connector; a first polymer layer over the first interconnection scheme, wherein the first polymer layer has a top surface coplanar with a top surface of the first semiconductor IC chip, a top surface of the first substrate of the first connector and a top surface of each of the plurality of first through vias; and a second interconnection scheme on the top surface of the first polymer layer, the top surface of the first semiconductor IC chip, the top surface of the first connector and the top surface of each of the plurality of first through vias, wherein the second interconnection scheme comprises a plurality of second metal contacts at a top surface of the chip package.

6. 发明申请

US20210043557A1 VERTICAL INTERCONNECT ELEVATOR BASED ON THROUGH SILICON VIAS 有权
公开(公告)号：US20210043557A1
公开(公告)日：2021-02-11
申请号：US16984663
申请日：2020-08-04
申请人： iCometrue Company Ltd.
发明人： Jin-Yuan Lee , Mou-Shiung Lin
IPC分类号： H01L23/528 , H01L23/522 , H01L23/532 , H01L23/00
摘要： A chip package includes a first integrated-circuit (IC) chip; a second integrated-circuit (IC) chip over the first integrated-circuit (IC) chip; a connector over the first integrated-circuit (IC) chip and on a same horizontal level as the second integrated-circuit (IC) chip, wherein the connector comprises a substrate over the first integrated-circuit (IC) chip and a plurality of through vias vertically extending through the substrate of the connector; a polymer layer over the first integrated-circuit (IC) chip, wherein the polymer layer has a portion between the second integrated-circuit (IC) chip and connector, wherein the polymer layer has a top surface coplanar with a top surface of the second integrated-circuit (IC) chip, a top surface of the substrate of the connector and a top surface of each of the plurality of through vias; and an interconnection scheme on the top surface of the polymer layer, the top surface of the second integrated-circuit (IC) chip, the top surface of the connector and the top surface of each of the plurality of through vias.

7. 发明申请

US20210005592A1 LOGIC DRIVE BASED ON MULTICHIP PACKAGE COMPRISING STANDARD COMMODITY FPGA IC CHIP WITH CRYPTOGRAPHY CIRCUITS 有权
公开(公告)号：US20210005592A1
公开(公告)日：2021-01-07
申请号：US16918909
申请日：2020-07-01
申请人： iCometrue Company Ltd.
发明人： Jin-Yuan Lee , Mou-Shiung Lin
IPC分类号： H01L25/18 , H01L23/538 , H03K19/17728 , H03K19/1776
摘要： A multichip package comprising: a first chip package comprising a first semiconductor IC chip, a first polymer layer in a space beyond and extending from a sidewall of the first semiconductor IC chip, a first through package via in the first polymer layer, and a first interconnection scheme under the first semiconductor IC chip, first polymer layer and first through package via, wherein the first semiconductor IC chip comprises a plurality of volatile memory cells configured to store first data associated with a plurality of resulting values for a look-up table (LUT) and a selection circuit configured to select, in accordance with a first input data set thereof, a data from a second input data set thereof as an output data for the logic operation; a first metal bump under the first chip package; and a non-volatile memory IC chip over the first chip package, wherein the non-volatile memory IC chip comprises a plurality of first non-volatile memory cells configured to store second data associated with the plurality of resulting values for the look-up table (LUT), wherein the first data are associated with the second data.

8. 发明申请

US20200186151A1 LOGIC DRIVE WITH BRAIN-LIKE ELASTICITY AND INTEGRALITY BASED ON STANDARD COMMODITY FPGA IC CHIPS USING NON-VOLATILE MEMORY CELLS 审中-公开
公开(公告)号：US20200186151A1
公开(公告)日：2020-06-11
申请号：US16791524
申请日：2020-02-14
申请人： iCometrue Company Ltd.
发明人： Jin-Yuan Lee , Mou-Shiung Lin
IPC分类号： H03K19/1776 , H03K19/17728 , H01L27/24 , H01L27/11517 , H01L25/18 , H01L23/538 , H01L23/00 , H03K19/173
摘要： A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

9. 发明授权

US10608642B2 Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells 有权
公开(公告)号：US10608642B2
公开(公告)日：2020-03-31
申请号：US16253206
申请日：2019-01-21
申请人： iCometrue Company Ltd.
发明人： Jin-Yuan Lee , Mou-Shiung Lin
IPC分类号： H03K19/177 , H01L25/00 , H03K19/1776 , H03K19/0948 , H01L25/18 , H01L27/24 , H01L27/22 , G11C11/412 , G11C11/16 , H01L23/538 , H01L23/00 , G11C11/419 , H03K19/20 , H03K19/173 , H01L45/00 , G11C13/00 , G11C14/00 , H03K19/17728 , H01L27/11 , H01L23/498 , H03K19/21
摘要： A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

10. 发明申请

US20200082885A1 LOGIC DRIVE USING STANDARD COMMODITY PROGRAMMABLE LOGIC IC CHIPS COMPRISING NON-VOLATILE RANDOM ACCESS MEMORY CELLS 审中-公开
公开(公告)号：US20200082885A1
公开(公告)日：2020-03-12
申请号：US16565967
申请日：2019-09-10
申请人： iCometrue Company Ltd.
发明人： Mou-Shiung Lin , Jin-Yuan Lee
IPC分类号： G11C14/00 , H01L23/14 , H01L23/538 , H01L23/498 , H01L25/18 , H01L23/00 , G11C11/16 , G11C13/00 , H01L27/22 , H01L45/00 , H01L23/528 , H01L23/522
摘要： A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC chip is configured to pass data associated with the output data for the logic operation to the second IC chip through the interposer.

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