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71. 发明授权

US11451220B2 Noise-tolerant delay circuit 有权
公开(公告)号：US11451220B2
公开(公告)日：2022-09-20
申请号：US17454207
申请日：2021-11-09
申请人： Silanna Asia Pte Ltd
发明人： Joseph H. Colles , Steven E. Rosenbaum , Stuart B. Molin
IPC分类号： H03K5/134 , H03K5/00 , H03K5/13
摘要： In a delay circuit, first and second sets of transistors are connected in series between a supply voltage and a ground. The first and second sets of transistors both include a current source transistor, a cascode transistor, and a control transistor. The first set of transistors generates a current that charges a capacitor to generate a ramp signal with a positive slope. A first bias transistor may cause the ramp signal to be biased to ground upon activating the first set of transistors. The second set of transistors generates a current that discharges the capacitor to generate the ramp signal with a negative slope. A second bias transistor may cause the ramp signal to be biased to the supply voltage upon activating the second set of transistors. The delay circuit transitions the state of the output signal based on a voltage level of the ramp signal.

72. 发明授权

US11444610B1 Variable frequency multiplier 有权
公开(公告)号：US11444610B1
公开(公告)日：2022-09-13
申请号：US17085958
申请日：2020-10-30
申请人： Keysight Technologies, Inc.
发明人： Alex Grichener , Naveed Edalati , Leonard M. Weber , Xiaohui Qin , Ryan Michael Avella , David Massie , Stuart Horsburgh , Cameron Blatter , Nicholas Brennan , Michael John Harriman , Andy Ferrara , Harrison Statham , Scott A. Hovland
IPC分类号： H03K5/00 , H03F3/19 , H03G5/16
摘要： A variable frequency multiplier circuit for frequency multiplying an input signal provided by an ultra-low phase noise signal source includes a tone generator configured to generate a multiple tones from the input signal; a signal separating circuit configured to separate the multiple tones into tones of interest and idler tones, where the tones of interest are separated into one or more groups and outputted from the signal separating circuit, and the idler tones are terminated; an amplification circuit configured to amplify each group of the tones of interest to optimize small and large signal responses; and a switched filter bank configured to selectively connect a selected tone from the tones of interest to a circuit output.

73. 发明授权

US11444603B2 Power control by direct drive 有权
公开(公告)号：US11444603B2
公开(公告)日：2022-09-13
申请号：US16888853
申请日：2020-06-01
申请人： King Kuen Hau
发明人： King Kuen Hau
IPC分类号： H03L5/00 , H03K3/012 , H02M1/08 , H02M3/06 , H03K5/00 , H03K19/0175 , H03H5/12 , G06G7/163 , H02M7/06 , H02M1/00 , H02M1/34
摘要： A power control circuit comprising a power supply and a load, the load being synthesized from an impedance synthesizer comprising two-terminal impedance elements connected in series and grouped in impedance modules. The impedance elements in each impedance module are of equal value, while those between the modules bear ratios uniquely defined according to the numbers of impedance elements in the impedance modules. A number of switches associated with said impedance elements short out a selected number of the impedance elements under the control of a first analog signal which may be preprocessed by an analytic function. The analog signal is converted to digital signals by an analog-to-digital converter, then level shifted to control the switches associated with the impedance elements, whereby the amount of power delivered to the load is controllable by the first analog signal. Pulse-width-modulation is deployed to further control the power by a second analog signal, with additional benefit of overload protection.

74. 发明授权

US11442800B2 Watchdog circuit systems 有权
公开(公告)号：US11442800B2
公开(公告)日：2022-09-13
申请号：US16985362
申请日：2020-08-05
申请人： Hamilton Sundstrand Corporation
发明人： Rajeeva Gopala Krishna , Shihab T. A. Muhammed
IPC分类号： G06F11/07 , G06F9/4401 , H03K3/037 , H03K21/08 , H03K5/00 , H03K5/19
摘要： A windowed watchdog circuit system can include a slow timer module configured to receive watchdog strobe signals from a processor and to determine whether a gap time between watchdog strobe signals is longer than a slow threshold time to output a slow threshold state when the gap time is longer than the slow threshold. The windowed watchdog circuit system can include a fast timer system configured to receive the watchdog strobe signals from the processor and to determine whether the gap time between watchdog strobe signals is shorter than a fast threshold time to output a fast threshold state when the gap time is shorted than the fast threshold. The windowed watchdog circuit system can be configured to output a reset state to reset the processor when any of the slow timer module and the fast timer system are outputting the slow threshold state or the fast threshold state, respectively.

75. 发明授权

US11437984B2 Delay circuit 有权
公开(公告)号：US11437984B2
公开(公告)日：2022-09-06
申请号：US17516726
申请日：2021-11-02
申请人： ABLIC Inc.
发明人： Shigeyuki Okabe
IPC分类号： H03K5/13 , H03K5/00
摘要： Delay circuit includes: first to fourth transistors; capacitor; constant current source; and resistor. The first transistor has a gate connected to an input terminal, a source connected to the first power supply terminal, and a drain. The second transistor has a gate connected to an input terminal and the gate of the first transistor, a drain connected to the drain of the first transistor and the second terminal of the capacitor, and a source. The third transistor has a gate connected to a node between the drain of the first transistor, the drain of the second transistor, and the second terminal of the capacitor, a source connected to the second power supply terminal, and a drain. The fourth transistor has a gate connected to the node and the gate of the third transistor, a drain connected to the drain of the third transistor and an output terminal, and a source.

76. 发明授权

US11424903B1 Drift tracking using an analog delay line during clock-data recovery 有权
公开(公告)号：US11424903B1
公开(公告)日：2022-08-23
申请号：US16987284
申请日：2020-08-06
申请人： Synopsys, Inc.
发明人： Marcin Pawel Kowalewski
IPC分类号： H04L7/00 , H03K5/1534 , H03K5/14 , H03K5/00
摘要： A clock recovery circuit may include a first circuit to produce an output signal that is a logical combination of an edge detection signal and a clock signal. At least some transitions in the edge detection signal may correspond to transitions in a set of data signals. The clock recovery circuit may also include a second circuit to average the output signal to produce a voltage, and a third circuit to add a variable delay to the clock signal based on the voltage.

77. 发明授权

US11386824B2 Display device and power management chip for the same 有权
公开(公告)号：US11386824B2
公开(公告)日：2022-07-12
申请号：US16623917
申请日：2019-10-16
申请人： WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
发明人： Rui Ju
IPC分类号： G09G5/00 , G09G3/20 , H03K3/012 , H03K3/3565 , H03K5/00
摘要： A display device and a power management chip are provided. The power management chip includes a rising-edge trigger, detecting rising edges of a pulse signal; a first counter, configured to calculate the number of the rising edges; a falling-edge trigger, detecting falling edges of the pulse signal; a second counter, configured to calculate the number of the falling edges of the pulse signal; an adder, configured to sum up the number of the rising edges and the number of the falling edges of the pulse signal; and a digital-to-analog converter, electrically connected to the adder, configured to convert to a target voltage based on the sum obtained by the adder. In such a way, the poweron time of the power management chip is reduced.

78. 发明授权

US11368125B2 Crystal oscillator reducing phase noise and semiconductor chip including the same 有权
公开(公告)号：US11368125B2
公开(公告)日：2022-06-21
申请号：US17340593
申请日：2021-06-07
申请人： Samsung Electronics Co., Ltd.
发明人： Jaehong Jung , Wonkang Kim , Seungjin Kim , Seunghyun Oh
IPC分类号： H03B5/36 , H03K5/159 , G06F1/10 , H03K5/00
摘要： A crystal oscillator reducing phase noise and a semiconductor chip including the same are provided. The crystal oscillator includes a transconductance circuit electrically connected to a crystal, a load capacitor connected to the transconductance circuit, a feedback resistance circuit connected between an input terminal of the transconductance circuit and an output terminal of the transconductance circuit, the feedback resistance circuit configured to provide a feedback resistance, and a variable resistance controller configured to generate a resistance control signal for controlling the feedback resistance, the resistance control signal causing the feedback resistance to have a first value in a first period and a second value in a second period, the first value being less than the second value, the first period corresponding to a first portion of a cycle of the clock signal, and the second period corresponding to a second portion of the cycle different from the first portion.

79. 发明授权

US11361788B2 Data path dynamic range optimization 有权
公开(公告)号：US11361788B2
公开(公告)日：2022-06-14
申请号：US16672718
申请日：2019-11-04
申请人： Seagate Technology LLC
发明人： Jason Bellorado , Marcus Marrow , Zheng Wu
IPC分类号： G11B5/596 , G11B20/10 , G06F13/10 , G06F13/42 , G06F1/08 , G06F1/12 , H04L25/03 , H03L7/093 , H03L7/095 , H03L7/07 , H03L7/081 , H03L7/091 , H04L7/00 , H04L7/033 , H03K5/131 , H03M1/00 , H03M13/41 , H03K5/135 , H03G3/20 , H03M1/12 , H03M13/29 , H04B1/7105 , H03K5/00
摘要： Systems and methods are disclosed for full utilization of a data path's dynamic range. In certain embodiments, an apparatus may comprise a circuit including a first filter to digitally filter and output a first signal, a second filter to digitally filter and output a second signal, a summing node, and a first adaptation circuit. The summing node combine the first signal and the second signal to generate a combined signal at a summing node output. The first adaptation circuit may be configured to receive the combined signal, and filter the first signal and the second signal to set a dynamic amplitude range of the combined signal at the summing node output by modifying a first coefficient of the first filter and a second coefficient of the second filter based on the combined signal.

80. 发明授权

US11356109B1 Wide-band frequency synthesizer for zero-IF WLAN radio transceiver and method thereof 有权
公开(公告)号：US11356109B1
公开(公告)日：2022-06-07
申请号：US17186120
申请日：2021-02-26
申请人： Realtek Semiconductor Corp.
发明人： Chia-Liang (Leon) Lin
IPC分类号： H03L7/185 , H03L7/197 , H03L7/099 , H03K5/00 , H03K21/00
摘要： A frequency synthesizer includes a clock multiplier unit configured to receive a first clock and output a second clock in accordance with a multiplication factor; a divide-by-three circuit configured to receive the second clock and output a third clock; a first divide-by-two circuit configured to receive the second clock and output a fourth clock; a second divide-by-two circuit configured to receive the fourth clock and output a fifth clock; a first multiplexer configured to receive the third clock and the fourth clock and output a seventh clock in accordance with a first selection signal; a second multiplexer configured to receive the third clock and the fifth clock and output an eighth clock in accordance with a second selection signal; and a mixer configured to receive the seventh clock and the eighth clock and output an output clock.

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