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81. 发明授权

US08487369B2 Semiconductor device with buried gates and buried bit lines and method for fabricating the same 失效
标题翻译：具有掩埋栅极和掩埋位线的半导体器件及其制造方法
公开(公告)号：US08487369B2
公开(公告)日：2013-07-16
申请号：US12833073
申请日：2010-07-09
申请人： Su-Young Kim
发明人： Su-Young Kim
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L27/10885 , H01L21/743 , H01L27/0207 , H01L27/10876
摘要： A semiconductor device includes: a plurality of first trenches formed inside a plurality of active regions; a plurality of buried gates configured to partially fill insides of the plurality of the first trenches; a plurality of second trenches formed to be extended in a direction crossing the plurality of the buried gates; and a plurality of buried bit lines configured to fill the plurality of the second trenches.
摘要翻译：半导体器件包括：形成在多个有源区域内的多个第一沟槽; 配置成部分地填充多个第一沟槽内部的多个掩埋栅极; 多个第二沟槽，形成为沿与所述多个所述掩埋栅极交叉的方向延伸; 以及配置成填充多个第二沟槽的多个埋入位线。

82. 发明授权

US08484585B2 Method for controlling pattern uniformity of semiconductor device 有权
标题翻译：控制半导体器件图案均匀性的方法
公开(公告)号：US08484585B2
公开(公告)日：2013-07-09
申请号：US12915570
申请日：2010-10-29
申请人： Duk Sun Han , Mi Hye Kim
发明人： Duk Sun Han , Mi Hye Kim
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method for controlling uniformity of patterns formed in a semiconductor device includes obtaining simulation contours with respect to respective cases while controlling a size of an outermost pattern and determining a size of the outermost pattern in which uniform distribution values (3σ) value of patterns included in the simulation contours satisfying specific conditions as a size of target outermost pattern.
摘要翻译：一种用于控制在半导体器件中形成的图案的均匀性的方法包括：在控制最外层图案的尺寸的同时，确定相对于各种情况的模拟轮廓，并且确定其中包含的图案的均匀分布值（3σ）值的最外图案的尺寸模拟轮廓满足特定条件作为目标最外层图案的尺寸。

83. 发明授权

US08482331B2 Open loop type delay locked loop and method for operating the same 失效
标题翻译：开环型延时锁定环及其操作方法
公开(公告)号：US08482331B2
公开(公告)日：2013-07-09
申请号：US12832549
申请日：2010-07-08
申请人： Seung-Joon Ahn , Jong-Chern Lee
发明人： Seung-Joon Ahn , Jong-Chern Lee
IPC分类号： H03H11/26
CPC分类号： H03K5/135 , H03K2005/00104
摘要： An open loop type delay locked loop includes a delay amount pulse generation unit configured to generate a delay amount pulse having a pulse width corresponding to a delay amount for delay locking a clock signal, a delay amount coding unit configured to output a code value by coding the delay amount in response to the delay amount pulse, a clock control unit configured to adjust a toggling period of the clock signal in response to a control signal, and a delay line configured to delay an adjusted clock signal outputted from the clock control unit in response to the code value.
摘要翻译：开环型延迟锁定环包括：延迟量脉冲生成单元，被配置为生成具有对应于用于延迟锁定时钟信号的延迟量的脉冲宽度的延迟量脉冲;延迟量编码单元，被配置为通过编码输出代码值延迟量响应于延迟量脉冲，时钟控制单元，被配置为响应于控制信号调整时钟信号的切换周期;以及延迟线，被配置为将从时钟控制单元输出的经调整的时钟信号延迟响应代码值。

84. 发明授权

US08476619B2 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08476619B2
公开(公告)日：2013-07-02
申请号：US12825805
申请日：2010-06-29
申请人： Ki-Beom Choe
发明人： Ki-Beom Choe
IPC分类号： H01L51/00
CPC分类号： H01L51/0562 , H01L51/0583
摘要： A semiconductor device includes a gate formed over a substrate, organic semiconductor pattern interposed between the substrate and the gate, junction regions formed in the substrate on both sides of the gate, and junction patterns formed over the junction regions to contact the organic semiconductor patterns.
摘要翻译：半导体器件包括形成在衬底上的栅极，介于衬底和栅极之间的有机半导体图案，形成在栅极两侧的衬底中的结区域以及形成在接合区域上以接触有机半导体图案的接合图案。

85. 发明授权

US08472263B2 Mode-register reading controller and semiconductor memory device 有权
标题翻译：模式寄存器读取控制器和半导体存储器件
公开(公告)号：US08472263B2
公开(公告)日：2013-06-25
申请号：US13410833
申请日：2012-03-02
申请人： Yin Jae Lee
发明人： Yin Jae Lee
IPC分类号： G11C16/04
CPC分类号： G11C7/1045
摘要： A semiconductor memory device may include a mode-register reading controller and a mode register. The mode-register reading controller generates a control signal for loading data into an input/output line in response to an enable signal, during a mode-register reading operation. The control signal is generated in response to a mode-register read signal when there is a reset command is input. The mode register loads the data into the input/output line in response to the control signal.
摘要翻译：半导体存储器件可以包括模式寄存器读取控制器和模式寄存器。模式寄存器读取控制器在模式寄存器读取操作期间产生用于响应于使能信号将数据加载到输入/输出线中的控制信号。当输入复位命令时，响应于模式寄存器读取信号产生控制信号。模式寄存器根据控制信号将数据加载到输入/输出线路中。

86. 发明授权

US08471318B2 Semiconductor device and method for forming using the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08471318B2
公开(公告)日：2013-06-25
申请号：US13176616
申请日：2011-07-05
申请人： Byung Sub Nam
发明人： Byung Sub Nam
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L21/76802 , H01L21/76831 , H01L27/0207 , H01L27/10885
摘要： A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a plurality of bit lines having a uniform width on a semiconductor substrate, an active region obliquely arranged to have a predetermined angle with respect to the bit lines, a spacer arranged around the bit lines connected to a center part of the active region. A contact pad is connected to a lower part of the bit lines. The spacer is formed not only at an upper part of sidewalls of the contact pad but also at sidewalls of the bit lines. As a result, a CD of the bit line contact increases, so that a bit line contact patterning margin also increases. A bit line pattern having a uniform width is formed so that a patterning margin increases. A storage electrode contact self-alignment margin increases so that a line-type storage electrode contact margin increases.
摘要翻译：公开了半导体器件及其形成方法。半导体器件包括在半导体衬底上具有均匀宽度的多个位线，相对于位线倾斜地布置成具有预定角度的有源区，围绕连接到活动的中心部分的位线布置的间隔件地区。接触焊盘连接到位线的下部。间隔件不仅形成在接触垫的侧壁的上部，而且形成在位线的侧壁处。结果，位线接触的CD增加，使得位线接触图案边缘也增加。形成具有均匀宽度的位线图形，使得图案化边缘增加。存储电极接触自对准边缘增加，使得线型存储电极接触边缘增加。

87. 发明授权

US08465908B2 Method for forming fine patterns of semiconductor device 失效
标题翻译：用于形成半导体器件精细图案的方法
公开(公告)号：US08465908B2
公开(公告)日：2013-06-18
申请号：US12272192
申请日：2008-11-17
申请人： Jae Seung Choi
发明人： Jae Seung Choi
IPC分类号： G03F7/20
CPC分类号： G03F7/0035 , G03F7/095 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L27/10894
摘要： A method for forming fine patterns of a semiconductor device employs a double patterning characteristic using a mask for forming a first pattern including a line pattern and a mask for separating the line pattern, and a reflow characteristic of a photoresist pattern.
摘要翻译：用于形成半导体器件的精细图案的方法采用双重图案化特征，使用用于形成包括线图案的第一图案的掩模和用于分离线图案的掩模，以及光致抗蚀剂图案的回流特性。

88. 发明申请

US20130147545A1 REFERENCE VOLTAGE GENERATION CIRCUIT AND INTERNAL VOLTAGE GENERATION CIRCUIT USING THE SAME 审中-公开
标题翻译：参考电压发生电路和内部电压发生电路
公开(公告)号：US20130147545A1
公开(公告)日：2013-06-13
申请号：US13452066
申请日：2012-04-20
申请人： Young Joo KIM
发明人： Young Joo KIM
IPC分类号： G05F3/02
CPC分类号： G11C5/147 , G11C29/12005
摘要： A reference voltage generation circuit includes a current source configured to generate a current by compensating for an internal temperature change, and output the generated current to an output node where a reference voltage is generated, and a resistor unit coupled to the output node and having a resistance value controlled in response to a control signal generated in a test mode.
摘要翻译：参考电压产生电路包括：电流源，被配置为通过补偿内部温度变化来产生电流，并将产生的电流输出到产生参考电压的输出节点;以及电阻器单元，耦合到输出节点并具有响应于在测试模式下产生的控制信号而控制电阻值。

89. 发明授权

US08461003B2 Method for fabricating 3D-nonvolatile memory device 失效
标题翻译：制造3D非易失性存储器件的方法
公开(公告)号：US08461003B2
公开(公告)日：2013-06-11
申请号：US13112767
申请日：2011-05-20
申请人： Han-Soo Joo , Sang-Hyun Oh , Yu-Jin Park
发明人： Han-Soo Joo , Sang-Hyun Oh , Yu-Jin Park
IPC分类号： H01L21/336
CPC分类号： H01L27/11556 , H01L27/1203
摘要： A method for fabricating a 3D-nonvolatile memory device includes forming a sub-channel over a substrate, forming a stacked layer over the substrate, the stacked layer including a plurality of interlayer dielectric layers that are alternatively stacked with conductive layers, selectively etching the stacked layer to form a first open region exposing the sub-channel, forming a main-channel conductive layer to gap-fill the first open region, selectively etching the stacked layer and the main-channel conductive layer to form a second open region defining a plurality of main channels, and forming an isolation layer to gap-fill the second open region.
摘要翻译：一种用于制造3D非易失性存储器件的方法，包括在衬底上形成子沟道，在衬底上形成堆叠层，所述堆叠层包括交替层叠有导电层的多个层间电介质层，选择性地蚀刻堆叠以形成暴露子通道的第一开放区域，形成主通道导电层以间隙填充第一开放区域，选择性地蚀刻堆叠层和主沟道导电层以形成限定多个的第二开口区域的主通道，并且形成隔离层以间隙填充第二开口区域。

90. 发明申请

US20130141976A1 Semiconductor Memory Apparatus 有权
公开(公告)号：US20130141976A1
公开(公告)日：2013-06-06
申请号：US13753623
申请日：2013-01-30
申请人： Hynix Semiconductor Inc.
发明人： Sung Bo Shim , Sang Don Lee , Jong Woo Kim
IPC分类号： G11C16/04
CPC分类号： G11C8/10 , G11C7/18 , G11C8/12 , G11C8/14 , G11C16/04 , G11C16/08
摘要： A semiconductor memory apparatus comprises first and second memory blocks each comprising semiconductor elements coupled to first and second local line groups, a first switching circuit configured to couple a first global line group to the first local line group of the first memory block in response to a block selection signal, a second switching circuit configured to couple a second global line group to the second local line groups of the first and second memory blocks in response to the block selection signal, and a third switching circuit configured to couple the first global line group to the first local line group of the second memory block in response to the block selection signal.

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