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81. 发明授权

US08025269B1 Chamber lid lifting apparatus 有权
标题翻译：室盖提升装置
公开(公告)号：US08025269B1
公开(公告)日：2011-09-27
申请号：US11975060
申请日：2007-10-16
申请人： Roger P. Sarver
发明人： Roger P. Sarver
IPC分类号： B66F3/10
CPC分类号： B66F15/00 , H01L21/67126 , H01L21/6719
摘要： A chamber lid lifting apparatus operable to lift a chamber lid of a semiconductor processing chamber is provided. The chamber lid lifting apparatus includes a handle. The handle includes a short end and a long end that together form a lever. The short end is operable to be temporarily coupled to a lid pivot point of the chamber lid. The long end is operable to transfer an applied force to the short end. The transferred force is operable to lift the chamber lid at the lid pivot point.
摘要翻译：提供可操作以提升半导体处理室的室盖的室盖提升装置。室盖提升装置包括手柄。手柄包括一起形成杠杆的短端和长端。短端可操作地临时联接到室盖的盖枢转点。长端可操作以将施加的力传递到短端。转移的力可操作以在盖枢转点处提升室盖。

82. 发明申请

US20110227547A1 Sensing capacitor for constant on-time and constant off-time switching regulators 审中-公开
标题翻译：用于恒定导通时间和恒定关断时间开关稳压器的感应电容器
公开(公告)号：US20110227547A1
公开(公告)日：2011-09-22
申请号：US12661646
申请日：2010-03-22
申请人： Lik-Kin Wong , Tze-Kau Man
发明人： Lik-Kin Wong , Tze-Kau Man
IPC分类号： G05F1/10
CPC分类号： H02M3/156
摘要： A method includes generating an output voltage using a constant on-time or constant off-time (COT) switching regulator. The switching regulator includes a switch and an output capacitor. The method also includes sensing a first current flowing through a sensing capacitor, where the first current is proportional to a second current flowing through the output capacitor. The method further includes controlling the switch based on the sensed first current. Controlling the switch could include generating a feedback voltage using the sensed first current, combining the feedback and output voltages to generate a combined voltage, comparing a scaled version of the combined voltage and a reference voltage, and triggering a one-shot timer based on the comparison. A capacitance of the output capacitor may be greater than a capacitance of the sensing capacitor by a factor of N, and a transimpedance amplifier having a gain based on N could generate the feedback voltage.
摘要翻译：一种方法包括使用恒定导通时间或恒定关断时间（COT）开关调节器产生输出电压。开关稳压器包括开关和输出电容器。该方法还包括感测流过感测电容器的第一电流，其中第一电流与流过输出电容器的第二电流成比例。该方法还包括基于感测的第一电流来控制开关。控制开关可以包括使用感测到的第一电流产生反馈电压，组合反馈和输出电压以产生组合电压，比较组合电压的缩放版本和参考电压，并且触发单触发计时器基于比较。输出电容器的电容可以大于感测电容器的电容乘以N，并且具有基于N的增益的跨阻抗放大器可以产生反馈电压。

83. 发明授权

US08023308B1 Non-volatile memory circuit using ferroelectric capacitor storage element 失效
标题翻译：使用铁电电容器存储元件的非易失性存储器电路
公开(公告)号：US08023308B1
公开(公告)日：2011-09-20
申请号：US07582615
申请日：1990-09-14
申请人： Joseph T. Evans, Jr. , William D. Miller , Richard H. Womack
发明人： Joseph T. Evans, Jr. , William D. Miller , Richard H. Womack
IPC分类号： G11C7/00 , G11C11/22
CPC分类号： G11C11/22 , G11C11/5657
摘要： A non-volatile memory cell and related system utilize ferroelectric capacitors as data storage elements. Circuitry is provided for writing to a single ferroelectric capacitor storage element, as well as to dual storage elements operating inversely. The storage elements are read by use of a sense amplifier in a configuration which automatically restores the original data states, thereby eliminating the need for a subsequent restore operation. Memory systems are described which include circuitry for driving bit lines, word lines and drive lines to accomplish both the write and read operations.
摘要翻译：非易失性存储单元及相关系统利用铁电电容器作为数据存储元件。提供电路用于写入单个铁电电容器存储元件以及反向运行的双重存储元件。通过使用自动恢复原始数据状态的配置的读出放大器来读取存储元件，从而不再需要后续的恢复操作。描述了包括用于驱动位线，字线和驱动线以实现写入和读取操作的电路的存储器系统。

84. 发明授权

US08022746B1 Bootstrap circuit for H-bridge structure utilizing N-channel high-side fets 有权
标题翻译：使用N沟道高边框架的H桥结构的自举电路
公开(公告)号：US08022746B1
公开(公告)日：2011-09-20
申请号：US12027781
申请日：2008-02-07
申请人： Barry Signoretti , David I. Anderson , Jianhui Zhang
发明人： Barry Signoretti , David I. Anderson , Jianhui Zhang
IPC分类号： H03K3/00
CPC分类号： H03K17/6871 , H02M1/08 , H03K2217/0045 , H03K2217/0063 , H03K2217/0081
摘要： The invention relates to an apparatus and method for driving high-side switching devices in an H-Bridge circuit. The apparatus includes first and second N-Channel high-side switching devices. Each of the high-side switching devices is associated with, and is selectively driven by, a driver circuit. Each of the driver circuits is associated with, and is powered from, a bootstrap capacitor. The apparatus further includes a cross-couple circuit that is arranged to charge each of the bootstrap capacitors based, at least in part, on whether the low-side switching device that is associated with the other bootstrap capacitor is open or closed.
摘要翻译：本发明涉及用于驱动H桥电路中的高侧开关装置的装置和方法。该装置包括第一和第二N沟道高侧开关装置。每个高侧开关装置与驱动器电路相关联并由驱动器电路选择性地驱动。每个驱动器电路与自举电容器相关联并由其自备电源。该装置还包括交叉耦合电路，其布置成用于至少部分地基于与另一自举电容器相关联的低侧开关装置是打开还是关闭来对每个自举电容器进行充电。

85. 发明授权

US08021042B1 Beta variation cancellation in temperature sensors 失效
标题翻译：温度传感器中的Beta变化消除
公开(公告)号：US08021042B1
公开(公告)日：2011-09-20
申请号：US12803289
申请日：2010-06-23
申请人： Mehmet Aslan , John W. Branch
发明人： Mehmet Aslan , John W. Branch
IPC分类号： G01K7/00 , H01L31/00
CPC分类号： G01K7/015
摘要： An apparatus and method for canceling variations in the beta for a bipolar junction transistor so that the diode equation can be employed to accurately measure the temperature of the transistor based at least in part on a ratio of two target collector currents and two measurements of the base-emitter voltage of the transistor. If the determined collector current of the transistor is relatively equivalent to one of the first and second target collector currents, the transistor's base-emitter voltage is measured and stored. An analog feedback circuit can be employed to change the determined collector current to be relatively equivalent to the first and second target collector currents. The analog feedback circuit can include an optional sample and hold component to further reduce power consumption and reduce noise. A digital circuit can be employed to change the determined collector current to be relatively equivalent to the first and second target collector currents. Additionally, the transistor can be remotely located in another integrated circuit.
摘要翻译：一种用于消除双极结型晶体管的β变化的装置和方法，使得可以采用二极管方程来至少部分地基于两个目标集电极电流和基极的两个测量值的比率精确地测量晶体管的温度 - 晶体管的发射极电压。如果所确定的晶体管的集电极电流相当于第一和第二目标集电极电流之一，则测量并存储晶体管的基极 - 发射极电压。可以采用模拟反馈电路来将所确定的集电极电流改变为相当于第一和第二目标集电极电流。模拟反馈电路可以包括可选的采样和保持组件，以进一步降低功耗并降低噪声。可以采用数字电路来将所确定的集电极电流改变为相当于第一和第二目标集电极电流。此外，晶体管可以远程位于另一个集成电路中。

86. 发明授权

US08004961B1 Independently configurable port redirection in a multi-port ethernet physical layer 有权
标题翻译：多端口以太网物理层中的独立配置端口重定向
公开(公告)号：US08004961B1
公开(公告)日：2011-08-23
申请号：US11529742
申请日：2006-09-28
申请人： Benjamin Clyde Buchanan , David Richard Rosselot
发明人： Benjamin Clyde Buchanan , David Richard Rosselot
IPC分类号： H04L12/28 , G06F15/177
CPC分类号： H04L45/24 , H04L45/22 , H04L49/351 , H04L49/357
摘要： A multi-port Ethernet Physical (PHY) layer device includes multiplexed datapaths and control logic such that each transmit data connection for a port may be mapped to any combination of the transmit data connections for one of multiple Media Access Control (MAC) layers, and each received data connection for a port may independently be mapped to an combination of the receive data connections for one of the MAC layers and the transmit data connection(s) for the other port(s). The device may be configured to operate in normal and port swap modes, to support failover switching and/or dedicated redundant connections, as a cable extender or media converter, as a snoop device, to form an Ethernet ring topology, for broadcast transmit or mirrored receive, or as a unidirectional repeater.
摘要翻译：多端口以太网物理层（PHY）层设备包括复用的数据路径和控制逻辑，使得用于端口的每个发送数据连接可被映射到多个媒体访问控制（MAC）层之一的发送数据连接的任何组合，以及用于端口的每个接收的数据连接可以独立地映射到MAC层之一的接收数据连接和用于另一个端口的发送数据连接的组合。该设备可以配置为在正常和端口交换模式下运行，以支持故障切换切换和/或专用冗余连接，作为电缆扩展器或媒体转换器作为监听设备，以形成以太网环形拓扑，用于广播发送或镜像接收或作为单向中继器。

87. 发明授权

US08001515B2 Simultaneous optimization of analog design parameters using a cost function of responses 有权
标题翻译：使用响应的成本函数同时优化模拟设计参数
公开(公告)号：US08001515B2
公开(公告)日：2011-08-16
申请号：US12004862
申请日：2007-12-21
申请人： Jang Dae Kim
发明人： Jang Dae Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F2217/08 , G06F2217/10 , G06F2217/16
摘要： An analog system consists of a multitude of interconnected components. Design of such a system involves optimization of the component parameters to achieve a target behavior, collectively called specification. The present invention provides a generic cost function for analog design optimization. It also provides cost surface modeling to speed up the optimization. The cost function compares the behavior of a design to a quantitative specification, which can be a ‘golden’ reference behavior (specification), and measures the error cost, an index of the behavioral discrepancy. That is, the target behavior is explicitly embedded in the cost function. By using the cost function, one can readily qualify a design and thereby identify good/optimum designs. The cost surface modeling with a Latin Hypercube Sampling design-of-experiment provides a statistical mathematical approximation of the actual design's error cost surface, speeding up the optimization by replacing the costly simulation of the actual design with mere evaluation of the mathematical cost surface model expression.
摘要翻译：模拟系统由多个互连组件组成。这种系统的设计涉及组件参数的优化以实现目标行为，统称为规范。本发明提供了用于模拟设计优化的通用成本函数。它还提供成本表面建模以加快优化。成本函数将设计的行为与定量规范进行比较，这可以是“黄金”参考行为（规范），并测量错误成本，这是行为差异的指标。也就是说，目标行为被明确地嵌入到成本函数中。通过使用成本函数，可以很容易地对设计进行限定，从而确定良好/最佳设计。拉丁超立方体采样设计实验的成本表面建模提供了实际设计的误差成本面的统计学数学近似，通过仅仅评估数学成本表面模型表达式代替实际设计的昂贵模拟来加快优化速度。

88. 发明授权

US07998791B2 Panel level methods and systems for packaging integrated circuits with integrated heat sinks 有权
标题翻译：用于集成散热器封装集成电路的面板级方法和系统
公开(公告)号：US07998791B2
公开(公告)日：2011-08-16
申请号：US12024918
申请日：2008-02-01
申请人： Sek Hoi Chong , Shee Min Yeong , Danny Cher Hau Koh , Eugene Kai Poh Wong
发明人： Sek Hoi Chong , Shee Min Yeong , Danny Cher Hau Koh , Eugene Kai Poh Wong
IPC分类号： H01L21/44
CPC分类号： H01L23/4334 , H01L21/561 , H01L21/568 , H01L23/3107 , H01L23/49548 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/73253 , H01L2224/73265 , H01L2224/83856 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , H01L2224/85 , H01L2224/83 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： Panel level methods and arrangements are described for attaching heat sinks in panel form with dice attached to a leadframe panel. Various methods produce integrated circuit packages each having an exposed heat sink on one outer surface of the package and an exposed die attach pad on a second opposite surface of the package.
摘要翻译：描述了面板级方法和布置，用于将面板形式的散热片连接到引线框板上。各种方法产生集成电路封装，每个集成电路封装每个在封装的一个外表面上具有暴露的散热器，以及在封装的第二相对表面上的裸露裸片附接焊盘。

89. 发明授权

US07989883B1 System and method for providing a poly cap and a no field oxide area to prevent formation of a vertical bird's beak structure in the manufacture of a semiconductor device 有权
标题翻译：用于提供聚盖和无场氧化物区域以防止在半导体器件的制造中形成垂直鸟嘴结构的系统和方法
公开(公告)号：US07989883B1
公开(公告)日：2011-08-02
申请号：US12321205
申请日：2009-01-16
申请人： Charles A. Dark , Andy Strachan
发明人： Charles A. Dark , Andy Strachan
IPC分类号： H01L29/66
CPC分类号： H01L21/763 , H01L21/76202
摘要： A system and method is disclosed that prevents the formation of a vertical bird's beak structure in the manufacture of a semiconductor device. A polysilicon filled trench is formed in a substrate of the semiconductor device. One or more composite layers are then applied over the trench and the substrate. A mask and etch process is then applied to etch the composite layers adjacent to the polysilicon filled trench. A field oxide process is applied to form field oxide portions in the substrate adjacent to the trench. Because no field oxide is placed over the trench there is no formation of a vertical bird's beak structure. A gate oxide layer is applied and a protection cap is formed over the polysilicon filled trench to protect the trench from unwanted effects of subsequent processing steps.
摘要翻译：公开了一种系统和方法，其防止在制造半导体器件时形成垂直鸟喙结构。在半导体器件的衬底中形成多晶硅填充沟槽。然后将一个或多个复合层施加在沟槽和衬底上。然后施加掩模和蚀刻工艺以蚀刻与多晶硅填充沟槽相邻的复合层。施加场氧化物工艺以在与沟槽相邻的衬底中形成场氧化物部分。由于没有将场氧化物放置在沟槽上，所以没有形成垂直鸟的喙结构。施加栅极氧化物层，并且在多晶硅填充的沟槽上形成保护帽，以保护沟槽免受后续处理步骤的不期望的影响。

90. 发明授权

US07982287B1 System and method for faceting the corners of a resistor protect layer to reduce vertical step height 有权
标题翻译：用于刻面电阻保护层角部的系统和方法，以减少垂直台阶高度
公开(公告)号：US07982287B1
公开(公告)日：2011-07-19
申请号：US12454050
申请日：2009-05-11
申请人： Rodney Hill
发明人： Rodney Hill
IPC分类号： H01L29/00
CPC分类号： H01L28/20 , H01L27/016
摘要： A system and method is disclosed for providing a resistor protect layer to protect a thin film resistor in a semiconductor device. A thin film resistor is formed on a dielectric layer and a resistor protect layer is placed over the thin film resistor. An etch procedure is employed to facet the corners of the resistor protect layer. The faceted corners of the resistor protect layer reduce the step height of the resistor protect layer. Then a conductor is deposited over the resistor protect layer and the dielectric layer. When portions of the conductor are subsequently etched away, the resistor protect layer protects the underlying thin film resistor from being exposed to the etch process.
摘要翻译：公开了一种用于提供电阻器保护层以保护半导体器件中的薄膜电阻器的系统和方法。在电介质层上形成薄膜电阻，在薄膜电阻上放置电阻保护层。采用蚀刻步骤来刻面电阻保护层的角部。电阻保护层的刻面角度降低了电阻保护层的台阶高度。然后将导体沉积在电阻器保护层和电介质层上。当导体的部分随后被蚀刻掉时，电阻器保护层保护下面的薄膜电阻不被暴露于蚀刻过程。

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