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81. 发明授权

US06859382B2 Memory array of a non-volatile ram 有权
标题翻译：非易失性RAM的内存阵列
公开(公告)号：US06859382B2
公开(公告)日：2005-02-22
申请号：US10249846
申请日：2003-05-12
申请人： Darrell Rinerson , Christophe J. Chevallier
发明人： Darrell Rinerson , Christophe J. Chevallier
IPC分类号： G11C11/56 , G11C13/00 , G11C16/02 , H01L21/8246 , H01L27/115 , H01L27/24 , H01L45/00 , G11C11/00
CPC分类号： G11C11/5685 , G11C11/5678 , G11C13/0004 , G11C13/0007 , G11C2213/31 , G11C2213/79 , H01L27/11502 , H01L27/11507 , H01L27/2409 , H01L27/2436 , H01L27/2445 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： Non-volatile memory cell with a single semiconductor device per memory cell. The present invention generally allows for a plurality of memory cells to be formed on a semiconductor substrate that supports a semiconductor device. A multi-resistive state material layer that changes its resistive state between a low resistive state and a high resistive state upon application of a voltage pulse is formed above the substrate, generally at a very high temperature. While the layers fabricated between the substrate and the multi-resistive state material use materials that can withstand high temperature processing, the layers fabricated above the multi-resistive state material do not need to withstand high temperature processing.
摘要翻译：每个存储单元具有单个半导体器件的非易失性存储器单元。本发明通常允许在支撑半导体器件的半导体衬底上形成多个存储单元。通常在非常高的温度下，在衬底上方形成在施加电压脉冲时改变其电阻状态在低电阻状态和高电阻状态之间的多电阻状态材料层。虽然在衬底和多电阻状态材料之间制造的层使用可承受高温处理的材料，但是在多电阻状态材料之上制造的层不需要经受高温处理。

82. 发明授权

US06850455B2 Multiplexor having a reference voltage on unselected lines 有权
标题翻译：多路复用器在未选择的线路上具有参考电压
公开(公告)号：US06850455B2
公开(公告)日：2005-02-01
申请号：US10330965
申请日：2002-12-26
申请人： Darrell Rinerson , Christophe J. Chevallier
发明人： Darrell Rinerson , Christophe J. Chevallier
IPC分类号： G11C13/00 , G11C8/00
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77
摘要： Providing a multiplexor outputting a reference voltage on unselected lines. A multiplexor that has at least one selected line and multiple unselected lines will have the unselected lines at a reference voltage. The selected line allows at least a portion of voltage to pass. Two gate circuits are used for each line, one that controls whether voltage (or a portion thereof) will pass, the other that connects the first gate circuit to a reference voltage, such as ground. In some embodiments the second gate circuit is always on, but is relatively small, such that the connection to the reference voltage has a weak effect on the output voltage. In other embodiments, the second gate circuit is only on when its associated first gate circuit is off.
摘要翻译：提供在未选择的线路上输出参考电压的多路复用器。具有至少一个选定行和多个未选择行的多路复用器将使未选择的行处于参考电压。所选择的线路允许至少一部分电压通过。每条线使用两个门电路，一个控制电压（或其一部分）是否通过，另一个将第一门电路连接到参考电压，例如接地。在一些实施例中，第二栅极电路总是导通，但是相对较小，使得与参考电压的连接对输出电压具有较弱的影响。在其他实施例中，第二门电路仅在其相关联的第一门电路断开时导通。

83. 发明授权

US06850429B2 Cross point memory array with memory plugs exhibiting a characteristic hysteresis 有权
标题翻译：具有显示特征滞后的存储插头的交叉点存储器阵列
公开(公告)号：US06850429B2
公开(公告)日：2005-02-01
申请号：US10330900
申请日：2002-12-26
申请人： Darrell Rinerson , Steven W. Longcor , Steve Kuo-Ren Hsia , Wayne Kinney , Edmond R. Ward , Christophe J. Chevallier
发明人： Darrell Rinerson , Steven W. Longcor , Steve Kuo-Ren Hsia , Wayne Kinney , Edmond R. Ward , Christophe J. Chevallier
IPC分类号： G11C11/56 , G11C13/00 , G11C11/00
CPC分类号： G11C13/0007 , G11C11/5685 , G11C2213/31 , G11C2213/77
摘要： Providing a cross point, memory array with memory plugs exhibiting a characteristic hysteresis. The memory plugs exhibit a hysteresis that, in the low resistive state, the first write threshold voltage is the point above which any voltages applied across the memory plug have substantially no effect on the resistive state and below which a voltage pulse will alter the resistance of the memory plug. Similarly, in the high resistive state, the second write threshold voltage is the point below which any voltages applied across the memory plug have substantially no effect on the resistive state and above which a voltage pulse will alter the resistance of the memory plug. The read voltages applied to the memory plug are typically above the first write threshold voltage and lower than the second write threshold voltage.
摘要翻译：提供交叉点，具有显示特征滞后的存储插件的存储器阵列。存储插头表现出滞后现象，在低电阻状态下，第一写入阈值电压是高于其上施加在存储器插头上的任何电压对电阻状态基本上没有影响的点，低于该电压脉冲将改变电阻内存插头。类似地，在高电阻状态下，第二写入阈值电压是低于施加在存储器插头上的任何电压对电阻状态基本上没有影响的点，并且高于该电压脉冲将改变存储器插头的电阻。施加到存储器插头的读取电压通常高于第一写入阈值电压并低于第二写入阈值电压。

84. 发明申请

US20040160807A1 Cross point memory array with memory plugs exhibiting a characteristic hysteresis 有权
标题翻译：具有显示特征滞后的存储插头的交叉点存储器阵列
公开(公告)号：US20040160807A1
公开(公告)日：2004-08-19
申请号：US10330900
申请日：2002-12-26
申请人： Unity Semiconductor Corporation
发明人： Darrell Rinerson , Steven W. Longcor , Steve Kuo-Ren Hsia , Wayne Kinney , Edmond R. Ward , Christophe J. Chevallier
IPC分类号： G11C011/00
CPC分类号： G11C13/0007 , G11C11/5685 , G11C2213/31 , G11C2213/77
摘要： Providing a cross point memory array with memory plugs exhibiting a characteristic hysteresis. The memory plugs exhibit a hysteresis that, in the low resistive state, the first write threshold voltage is the point above which any voltages applied across the memory plug have substantially no effect on the resistive state and below which a voltage pulse will alter the resistance of the memory plug. Similarly, in the high resistive state, the second write threshold voltage is the point below which any voltages applied across the memory plug have substantially no effect on the resistive state and above which a voltage pulse will alter the resistance of the memory plug. The read voltages applied to the memory plug are typically above the first write threshold voltage and lower than the second write threshold voltage.
摘要翻译：提供具有表现出特征滞后的存储插件的交叉点存储器阵列。存储插头表现出滞后现象，在低电阻状态下，第一写入阈值电压是高于其上施加在存储器插头上的任何电压对电阻状态基本上没有影响的点，并且低于该电压脉冲将改变电阻内存插头。类似地，在高电阻状态下，第二写入阈值电压是低于施加在存储器插头上的任何电压对电阻状态基本上没有影响的点，并且高于该电压脉冲将改变存储器插头的电阻。施加到存储器插头的读取电压通常高于第一写入阈值电压并低于第二写入阈值电压。

85. 发明授权

US10622028B2 Local bit lines and methods of selecting the same to access memory elements in cross-point arrays 有权
公开(公告)号：US10622028B2
公开(公告)日：2020-04-14
申请号：US15984107
申请日：2018-05-18
申请人： Unity Semiconductor Corporation
发明人： Chang Hua Siau , Christophe Chevallier , Darrell Rinerson , Seow Fong Lim , Sri Rama Namala
IPC分类号： G11C5/02 , G11C13/00 , G11C8/00 , G11C11/00 , H01L21/82 , H01L45/00 , H01L27/24
CPC分类号： G11C5/025 , G11C5/02 , G11C8/00 , G11C11/00 , G11C13/0002 , G11C13/004 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0061 , G11C13/0069 , G11C13/0097 , H01L21/82 , H01L45/16 , G11C2213/77 , H01L27/2481
摘要： Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

86. 发明授权

US10347332B2 High voltage switching circuitry for a cross-point array 有权
公开(公告)号：US10347332B2
公开(公告)日：2019-07-09
申请号：US16004705
申请日：2018-06-11
申请人： Unity Semiconductor Corporation
发明人： Christophe Chevallier , Chang Hua Siau
IPC分类号： G11C11/00 , G11C13/00 , G11C8/08 , G11C8/10 , H03K3/356 , H03K19/0185
摘要： A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array.

87. 发明授权

US09767897B2 Conductive metal oxide structures in non-volatile re-writable memory devices 有权
公开(公告)号：US09767897B2
公开(公告)日：2017-09-19
申请号：US15075754
申请日：2016-03-21
申请人： Unity Semiconductor Corporation
发明人： Lawrence Schloss , Julie Casperson Brewer , Wayne Kinney , Rene Meyer
IPC分类号： G11C13/00 , G11C11/56 , H01L27/24 , H01L45/00
CPC分类号： G11C13/0026 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C2013/0045 , G11C2013/0073 , G11C2213/31 , G11C2213/32 , G11C2213/56 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/24 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/147
摘要： A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

88. 发明授权

US09691821B2 Vertical cross-point arrays for ultra-high-density memory applications 有权
公开(公告)号：US09691821B2
公开(公告)日：2017-06-27
申请号：US15095542
申请日：2016-04-11
申请人： Unity Semiconductor Corporation
发明人： Bruce Lynn Bateman
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L27/249 , H01L27/2418 , H01L27/2454 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/147
摘要： An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

89. 发明授权

US09570515B2 Memory element with a reactive metal layer 有权
标题翻译：具有反应性金属层的记忆元件
公开(公告)号：US09570515B2
公开(公告)日：2017-02-14
申请号：US14850702
申请日：2015-09-10
申请人： Unity Semiconductor Corporation
发明人： Christophe J. Chevallier , Steve Kuo-Ren Hsia , Wayne Kinney , Steven Longcor , Darrell Rinerson , John Sanchez , Philip F. S. Swab , Edmond R. Ward
IPC分类号： H01L27/24 , H01L45/00 , G11C11/16 , G11C11/56 , G11C13/00
CPC分类号： H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
摘要： A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
摘要翻译：公开了一种包括导电氧化物电极的存储单元。存储单元包括用于将数据存储为多个电阻状态的存储元件。存储元件包括与可包括一层或多层材料的电极接触的导电金属氧化物（CMO）（例如，钙钛矿）层。这些材料层中的至少一层可以是与CMO接触的导电氧化物（例如，诸如LaSrCoO3-LSCoO或LaNiO3-LNO的钙钛矿）。可以选择导电氧化物层作为晶种层，以为CMO提供良好的晶格匹配和/或较低的结晶温度。导电氧化物层也可以与金属层（例如Pt）接触。存储单元还具有非线性IV特性，这在某些阵列中是有利的，例如非易失性两端交叉点存储阵列。

90. 发明授权

US09390796B2 Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations 有权
公开(公告)号：US09390796B2
公开(公告)日：2016-07-12
申请号：US14790430
申请日：2015-07-02
申请人： UNITY SEMICONDUCTOR CORPORATION
发明人： Chang Hua Siau , Bruce Lynn Bateman
IPC分类号： G11C5/06 , G11C13/00 , G11C5/08 , G11C7/00 , G11C7/18 , G11C7/04 , G11C7/12 , G11C16/24
CPC分类号： G11C5/06 , G11C5/08 , G11C7/00 , G11C7/04 , G11C7/12 , G11C7/18 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0026 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C16/24 , G11C2213/71
摘要： A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

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