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1. 发明申请

US20230139283A1 MEMORY WITH EFFICIENT DVS CONTROLLED BY ASYNCHRONOUS INPUTS 有权
公开(公告)号：US20230139283A1
公开(公告)日：2023-05-04
申请号：US17517386
申请日：2021-11-02
申请人： QUALCOMM Incorporated
发明人： Pradeep RAJ , Rahul SAHU , Sharad Kumar GUPTA , Chulmin JUNG
IPC分类号： G11C29/50 , G11C8/08
摘要： A memory is provided that is configured to practice a sleep mode without retention in which a both bitcell array and a memory periphery are powered down responsive to an assertion of sleep mode without retention control signal. The sleep mode without retention control signal is also asserted during a DVS scan to power down the bitcell array. The memory includes a power management circuit that responds to an assertion of a DVS scan control signal to prevent the assertion of the sleep mode without retention control signal from causing a power down of the memory periphery during the DVS scan. The memory periphery may thus be thoroughly tested by the DVS scan because leakage current from the bitcell array is prevented by the powering down of the bitcell array.

2. 发明授权

US11636887B2 Semiconductor device having dummy lines electrically connected with each other 有权
公开(公告)号：US11636887B2
公开(公告)日：2023-04-25
申请号：US17359223
申请日：2021-06-25
申请人： SK hynix Inc.
发明人： Byung In Kang , Nak Kyu Park , Han Kyu Lee
IPC分类号： G11C8/14 , G11C8/10 , G11C8/08 , G11C7/06
摘要： A semiconductor device may include a memory bank, an X-decoder adjacent to the memory bank in a row direction, a Y-decoder adjacent to the memory bank in a column direction, X-lines extending from the X-decoder across the memory bank in the row direction, Y-lines extending from the Y-decoder across the memory bank in the column direction, and a plurality of connection lines.

3. 发明授权

US11626164B2 Voltage supply circuit, memory cell arrangement, and method for operating a memory cell arrangement 有权
公开(公告)号：US11626164B2
公开(公告)日：2023-04-11
申请号：US17744473
申请日：2022-05-13
申请人： Ferroelectric Memory GmbH
发明人： Marko Noack
IPC分类号： G11C16/12 , G11C16/26 , G11C5/14 , G11C7/10 , G11C11/22 , G11C16/30 , G11C8/08 , G11C7/12
摘要： In various aspects, a method for operating a memory cell arrangement is provided, including: providing a set of supply voltages to one or more sets of memory cell drivers to write one or more memory cells of the memory cell arrangement; wherein providing the set of supply voltages includes: ramping a first supply voltage of the set of supply voltages to a first predefined output voltage level, and ramping a second supply voltage of the set of supply voltages to a second predefined output voltage level dependent upon the first supply voltage, the first predefined output voltage level and the second predefined output voltage level defining a first predefined ratio, wherein, during the ramping of the first supply voltage and of the second supply voltage, a first ratio of the first supply voltage to the second supply voltage is substantially equal to or less than the first predefined ratio.

4. 发明申请

US20230096616A1 STORAGE DEVICE AND MANUFACTURING METHOD THEREOF 有权
公开(公告)号：US20230096616A1
公开(公告)日：2023-03-30
申请号：US17542427
申请日：2021-12-05
申请人： WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Jongbae JEONG
IPC分类号： H01L27/11519 , H01L27/11565 , G11C8/10 , G11C8/08 , G11C7/18 , G11C8/14
摘要： A storage device and a manufacturing method thereof are provided. The storage device includes a first chip and a second chip. The second chip is stacked on the first chip in a third direction. The first chip includes a storage array, and the storage array includes at least one storage block. An occupied area after the first chip and the second chip are stacked can be reduced by constructing a first local bit line decoder block, a second local bit line decoder block, a first word line decoder block, and a second local bit line decoder block in a top view projection area, thereby reducing plane occupied space of the storage device. This is beneficial for minimizing the size of the storage device.

5. 发明授权

US11610612B2 High speed SRAM using enhance wordline/global buffer drive 有权
公开(公告)号：US11610612B2
公开(公告)日：2023-03-21
申请号：US17375149
申请日：2021-07-14
申请人： STMicroelectronics International N.V.
发明人： Ashish Kumar , Dipti Arya
IPC分类号： G11C7/10 , G11C7/22 , G11C5/14 , G11C8/08
摘要： A row decoder includes decoder logic generating an initial word line signal, and two inverters. The first inverter is formed by a first p-channel transistor having a source coupled to a supply voltage and a gate receiving the initial word line signal. The second inverter is formed by a first n-channel transistor having a drain coupled to a drain of the first p-channel transistor, a source coupled to a shared ground line, and a gate receiving the initial word line signal. An inverse word line signal is generated at the drain of the first n-channel transistor. A second inverter inverts the inverse word line signal to produce a word line signal. Negative bias generation circuitry generates a negative bias voltage on the shared ground line when the initial word line signal is logic high, and otherwise couples the shared ground line to ground.

6. 发明申请

US20230071992A1 MEMORY DEVICE INCLUDING A PASS TRANSISTOR CIRCUIT AND A DISCHARGE TRANSISTOR CIRCUIT 有权
公开(公告)号：US20230071992A1
公开(公告)日：2023-03-09
申请号：US17674829
申请日：2022-02-17
申请人： SK hynix Inc.
发明人： Sang Hyun SUNG , Jin Ho KIM , Sung Lae OH
IPC分类号： G11C5/06 , G11C5/02 , G11C8/10 , G11C8/12 , G11C8/08
摘要： A memory device includes a pass transistor circuit included in a first wafer, and configured to transfer an operating voltage to row lines of a memory cell array; and a discharge transistor circuit included in a second wafer that overlaps with the first wafer in a vertical direction, and configured to transfer a discharge voltage to at least one of the row lines.

7. 发明授权

US11600320B2 Perpectual digital perceptron 有权
公开(公告)号：US11600320B2
公开(公告)日：2023-03-07
申请号：US16717444
申请日：2019-12-17
申请人： FlashSilicon Incorporation
发明人： Lee Wang
IPC分类号： G11C8/08 , G11C15/04 , G06N3/063 , G06N3/08 , G11C11/54
摘要： An in-memory digital processor, Perpetual Digital Perceptron (PDP), is disclosed. The digital in-memory processor of the invention processes the input digital information according to a database of the digital content data stored/hardwired in the Content Read Only Memory (CROM) array and outputs the correspondent digital response data stored/hardwired in the Response Read Only Memory (RROM) array. The PDP is the hardwired digital in-memory processor without re-configuration capability and similar to the instinct functions of biological hardwired brains without re-shaping their neuromorphic structures from training and learning.

8. 发明授权

US11599299B2 3D memory circuit 有权
公开(公告)号：US11599299B2
公开(公告)日：2023-03-07
申请号：US17098299
申请日：2020-11-13
申请人： Invensas LLC
发明人： Javier A. DeLaCruz , David E. Fisch
IPC分类号： G11C13/00 , G06F3/06 , G11C8/08 , G11C8/14 , G11C5/02 , H01L25/065 , G11C11/408 , G11C16/08 , G11C7/10
摘要： Some embodiments provide a three-dimensional (3D) circuit that has data lines of one or more memory circuits on a different IC die than the IC die(s) on which the memory blocks of the memory circuit(s) are defined. In some embodiments, the 3D circuit includes a first IC die with a first set of two or more memory blocks that have a first set of data lines. The 3D circuit also includes a second IC die that is stacked with the first IC dies and that includes a second set of two or more memory blocks with a second set of data lines. The 3D circuit further includes a third IC die that is stacked with the first and second IC dies and that includes a third set of data lines, which connect through several z-axis connections with the first and second sets of data lines to carry data to and from the first and second memory block sets when data is being written to and read from the first and second memory block sets. The z-axis connections in some embodiments electrically connect circuit nodes in overlapping portions of the first and third IC dies, and overlapping portions of second and third IC dies, in order to carry data between the third set of data lines on the third IC die and the first and second set of data lines of the first and second of memory block sets on the first and second IC dies. These z-axis connections between the dies are very short as the dies are very thin. For instance, in some embodiments, the z-axis connections are less than 10 or 20 microns. The z-axis connections are through silicon vias (TSVs) in some embodiments.

9. 发明申请

US20230063400A1 LOW_POWERED MEMORY DEVICE AND METHOD OF CONTROLLING POWER OF THE SAME 有权
公开(公告)号：US20230063400A1
公开(公告)日：2023-03-02
申请号：US17865381
申请日：2022-07-14
申请人： METACNI CO., LTD.
发明人： Young Seung KIM , Min Chul JUNG , Scott Seung Moon YOO
IPC分类号： G11C7/10 , G11C7/12 , G11C8/08 , G11C5/02
摘要： The memory device according to an embodiment may comprise a memory cell array in which memory cells of a latch structure are connected in a matrix form to word lines and bit lines and a peripheral circuit configured to supply a first voltage to the memory cells only in a developing section of a read operation for the memory cells and supply a second voltage which maintains data of the memory cells and lower than the first voltage in other sections. The peripheral circuit may be configured to supply the second voltage to the memory cells in all sections of a write operation for the memory cells.

10. 发明申请

US20230027165A1 WORDLINE SYSTEM ARCHITECTURE SUPPORTING ERASE OPERATION AND I-V CHARACTERIZATION 有权
公开(公告)号：US20230027165A1
公开(公告)日：2023-01-26
申请号：US17380688
申请日：2021-07-20
申请人： GLOBALFOUNDRIES U.S. Inc.
发明人： Ramesh RAGHAVAN , Balaji JAYARAMAN , Ming YIN
IPC分类号： G11C29/50 , G11C7/12 , G11C8/08
摘要： The present disclosure relates to integrated circuits, and more particularly, to a wordline system architecture supporting an erase operation and current-voltage (I-V) characterization and methods of manufacture and operation. In particular, the present disclosure relates to a structure including: a twin cell circuit which is connected to a wordline of a memory array; a sourceline driver which is connected to a sourceline of the memory array for providing a cell level current-voltage (I-V) access of the twin cell circuit; and an integrated analog multiplexor which is connected to the twin cell circuit.

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