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81. 发明授权

US08654626B2 Packet sorting device, receiving device and packet sorting method 失效
标题翻译：分组分类装置，接收装置和分组分类方法
公开(公告)号：US08654626B2
公开(公告)日：2014-02-18
申请号：US13198630
申请日：2011-08-04
申请人： Kiyohisa Ichino , Norio Yamagaki
发明人： Kiyohisa Ichino , Norio Yamagaki
IPC分类号： G01R31/08 , H04L12/28 , H04L12/54 , G06F15/16 , G06F15/173 , G06F11/00 , G06F3/00
CPC分类号： H04L47/6205
摘要： A packet sorting device includes: a buffer for storing packets belonging to a plurality of communication flows; and a control section which determines, when receiving one of a series of packets, whether the one of the received packets is a disorder packet by a determination process, and sorts the received packets in a correct order by storing the disorder packet and communication flow information thereof in the buffer so that the disorder packet and communication flow identification information are correlated. The disorder packet is one of the received packets which is received in an order different from a transmission order of the packets. The communication flow information identifies the plurality of communication flows.
摘要翻译：一种分组分类装置，包括：存储属于多个通信流的分组的缓冲器; 以及控制部，当通过确定处理接收到一系列分组中的一个时，确定所接收的分组中的一个是无序分组，并且通过存储无序分组和通信流信息来以正确的顺序对接收的分组进行排序在缓冲器中使无序分组和通信流识别信息相关。无序分组是以与分组的传输顺序不同的顺序接收的接收分组之一。通信流信息识别多个通信流。

82. 发明授权

US08651667B2 Projector and method of controlling the same 有权
标题翻译：投影机及其控制方法
公开(公告)号：US08651667B2
公开(公告)日：2014-02-18
申请号：US12737530
申请日：2008-08-12
申请人： Atsushi Katou
发明人： Atsushi Katou
IPC分类号： G03B21/00
CPC分类号： G09G3/002 , G02B26/008 , G03B21/2033 , G03B21/2066 , G03B33/00 , G03B37/04 , G09G2300/026 , G09G2310/0235
摘要： The present invention is applied to a projector that comprises a plurality of projection devices which generate images by modulating laser beams in the colors of R, G, B with optical modulators and which project the images onto projection surfaces through projection lenses, wherein the images projected respectively from said projection devices onto said projection surfaces are tiled into a single image as a whole. In the projector of the present invention, the number of G-color laser beam sources is smaller than the number of images projected respectively from said projection devices onto said projection surfaces; and said projection devices share said G-color laser beam sources and apply G-color laser beams emitted from said G-color laser beam sources to said optical modulators thereof.
摘要翻译：本发明应用于投影仪，其包括通过用光学调制器调制R，G，B的颜色的激光束而产生图像的多个投影装置，并且通过投影透镜将图像投影到投影表面上，其中投影的图像分别从所述投影装置到所述投影表面上整体地平铺成单个图像。在本发明的投影仪中，G色激光束源的数量小于从所述投影装置投影到所述投影面上的图像数; 并且所述投影装置共享所述G色激光束源，并将从所述G色激光束源发射的G色激光束应用于其所述光调制器。

83. 发明授权

US08643103B2 Semiconductor device including gate contact region and protruding gate electrode 有权
标题翻译：半导体器件包括栅极接触区域和突出栅电极
公开(公告)号：US08643103B2
公开(公告)日：2014-02-04
申请号：US13244445
申请日：2011-09-24
申请人： Yoshiya Kawashima
发明人： Yoshiya Kawashima
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0696 , H01L29/0869 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/7811
摘要： A semiconductor device for preventing an outer well from being separated by a trench gate electrode from the well of a cell region while suppressing increase in the gate resistance in which buried gate electrodes extending in a direction overlapping a gate contact region extend only before a gate electrode so as not to overlap the gate electrode, the source contact situated between each of the buried gate electrodes is shorter than the buried gate electrode in the vertical direction, the ends of the buried gate electrodes on the side of the gate electrode are connected with each other by a buried connecting electrode disposed before the gate electrode, the buried connecting electrode extends in a direction parallel with the longer side of the semiconductor device, and is not connected to the buried gate electrode on the side of the contact situated adjacent to the contact-side buried gate electrode.
摘要翻译：一种半导体器件，用于防止外部阱被单元区域的阱分离，同时抑制栅极电阻的增加，其中在与栅极接触区域重叠的方向上延伸的掩埋栅电极仅在栅电极之前延伸为了不与栅电极重叠，位于每个掩埋栅电极之间的源极触点在垂直方向上比掩埋栅电极短，栅电极一侧的掩埋栅电极的端部与每个另外，通过设置在栅电极之前的埋置连接电极，埋入连接电极在与半导体器件的长边平行的方向上延伸，并且不与位于邻近触点的触点侧的掩埋栅极连接侧埋电极。

84. 发明授权

US08640069B2 Noise analysis model and noise analysis method including disposing resistors and setting points in a semiconductor 有权
标题翻译：噪声分析模型和噪声分析方法，包括在半导体中设置电阻和设定点
公开(公告)号：US08640069B2
公开(公告)日：2014-01-28
申请号：US13546985
申请日：2012-07-11
申请人： Masaaki Soda
发明人： Masaaki Soda
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F2217/82
摘要： Provided is a noise analysis model and a noise analysis method that can analyze effects of substrate noise on each of elements included in a circuit to be analyzed. The noise analysis model includes first to third resistors. The first resistor serves as a substrate resistor in a semiconductor substrate between a first point set in the semiconductor substrate between a noise source and a transistor to which substrate noise from the noise source propagates through the semiconductor substrate and a second point set in the semiconductor substrate just below a back gate of the transistor. The second resistor serves as a substrate resistor in the semiconductor substrate between the second point and a fixed potential region near the transistor. The third resistor serves as a line resistor of a line connecting the fixed potential region and a power pad that supplies a ground potential.
摘要翻译：提供了可以分析衬底噪声对要分析的电路中的每个元件的影响的噪声分析模型和噪声分析方法。噪声分析模型包括第一至第三电阻。第一电阻器用作半导体衬底中的衬底电阻器，位于半导体衬底中的噪声源和来自噪声源的衬底噪声通过半导体衬底传播的晶体管之间的第一点和设置在半导体衬底中的第二点恰好在晶体管的背栅之下。第二电阻器用作第二点和晶体管附近的固定电位区域之间的半导体衬底中的衬底电阻器。第三电阻器用作连接固定电位区域的线路电阻器和提供地电位的功率垫片。

85. 发明授权

US08635927B2 Speed change device of a transmission 有权
标题翻译：变速器变速装置
公开(公告)号：US08635927B2
公开(公告)日：2014-01-28
申请号：US12735442
申请日：2009-02-06
申请人： Kouhei Akashi , Tadashi Ikeda
发明人： Kouhei Akashi , Tadashi Ikeda
IPC分类号： B60K20/00 , F16H59/04
CPC分类号： F16H63/18 , F16H61/28 , F16H61/32 , F16H2061/2869 , F16H2061/2884 , F16H2063/025
摘要： A speed change device for shifting the gear of a transmission by using a cylindrical drum that reciprocally moves and rotates, featuring the structure of a compact size and excellent operability. To execute the shifting operation, the speed change device of the invention uses a cylindrical drum 4 that reciprocally moves in the axial direction and is rotatably supported. Fork pins FP1 to FP4 coupled to a plurality of forks of the transmission are fitted into drum grooves 41 to 44 formed in the cylindrical surface of the cylindrical drum. In each drum groove, there are formed small width portions of a width nearly equal to that of the fork pin and large width portions wider than the small width portions in a manner that the fork pin positioned at the small width portion is shifted. To shift the gear, the cylindrical drum 4 is rotated by a select motor 6 to select the fork pin positioned at the small width portion. Next, a threaded shaft 1 is rotated by a shift motor 7 to move the cylindrical drum 4 in the axial direction to thereby shift the selected fork pin.
摘要翻译：一种变速装置，其通过使用往复移动和旋转的圆柱形鼓来移动变速器的齿轮，具有紧凑的尺寸和优异的可操作性的结构。为了执行换档操作，本发明的变速装置使用沿轴向往复移动并被可旋转地支撑的圆筒形滚筒4。联接到传动装置的多个叉的叉销FP1至FP4装配到形成在圆筒形滚筒的圆柱形表面中的滚筒槽41至44中。在每个鼓槽中，形成宽度大致等于叉销宽度的宽度较小的宽度部分，宽度小的部分以小宽度部分的叉销偏移的方式形成。为了移动齿轮，圆筒形滚筒4由选择马达6旋转以选择位于小宽度部分的叉销。接下来，螺纹轴1通过换档马达7旋转，以使圆柱形滚筒4沿轴向方向移动，从而移动所选择的叉销。

86. 发明授权

US08627570B2 Roller thrust bearing cage and manufacturing method thereof 有权
标题翻译：滚子推力轴承保持架及其制造方法
公开(公告)号：US08627570B2
公开(公告)日：2014-01-14
申请号：US12923791
申请日：2010-10-07
申请人： Wataru Takamizawa
发明人： Wataru Takamizawa
IPC分类号： B21D53/12 , B21K1/05
CPC分类号： F16C33/4682 , F16C19/305 , F16C33/4635 , F16C33/543 , Y10T29/49636 , Y10T29/49691
摘要： A manufacturing method of a roller bearing cage, including a cage main body formed with an annular plate, and a plurality of cage pockets opened along a circumferential direction on the cage main body for retaining rollers having flat end faces, includes punching an annular plate from a metal, forming a plurality of cage pockets on the annular plate, and pressing an edge of one of the cage pockets in a thickness direction of the annular plate on a side face of the one of the cage pockets with a press jig having a pressing face of a predetermined shape to form a chamfered portion.
摘要翻译：一种滚子轴承保持架的制造方法，包括形成有环形板的保持架主体和沿着保持架主体的周向开放的多个保持架，用于保持具有平坦端面的辊，包括：将金属，在所述环形板上形成多个保持架袋，并且在所述一个所述保持箱的侧面上沿着所述环形板的厚度方向的一个所述保持箱的边缘，面以形成倒角部。

87. 发明授权

US08624328B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08624328B2
公开(公告)日：2014-01-07
申请号：US12591089
申请日：2009-11-06
申请人： Jun Kawahara , Yoshihiro Hayashi , Ippei Kume
发明人： Jun Kawahara , Yoshihiro Hayashi , Ippei Kume
IPC分类号： H01L27/06
CPC分类号： H01L27/0207 , H01L23/522 , H01L23/5223 , H01L23/53238 , H01L23/53295 , H01L27/10814 , H01L27/10852 , H01L27/10894 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device including: a semiconductor substrate; a multi-layered wiring structure which is formed over the semiconductor substrate and in which a plurality of wiring layers, each of which is formed by a wiring and an insulating layer, are laminated; and a capacitive element having a lower electrode, a capacitor insulating layer, and an upper electrode which is embedded in the multi-layered wiring structure, wherein at least two or more of the wiring layers are provided between a lower capacitor wiring connected to the lower electrode and an upper capacitor wiring connected to the upper electrode.
摘要翻译：提供一种半导体器件，包括：半导体衬底; 形成在半导体衬底上并且其中由布线和绝缘层形成的多个布线层被层叠的多层布线结构; 以及具有嵌入在所述多层布线结构中的下电极，电容绝缘层和上电极的电容元件，其特征在于，所述布线层中的至少两个以上设置在与所述下层电极电极和连接到上电极的上电容器布线。

88. 发明授权

US08621262B2 Semiconductor integrated circuit and method for controlling semiconductor integrated circuit 有权
标题翻译：半导体集成电路及半导体集成电路控制方法
公开(公告)号：US08621262B2
公开(公告)日：2013-12-31
申请号：US13619403
申请日：2012-09-14
申请人： Shigeyuki Ueno , Hiroyuki Nakajima
发明人： Shigeyuki Ueno , Hiroyuki Nakajima
IPC分类号： G06F11/00
CPC分类号： G06F13/362 , G06F15/7807
摘要： A semiconductor integrated circuit, including a first master circuit, a second master circuit, a first slave circuit assigned to the first master circuit, and determines that an access request signal is sent from the first master circuit when an identification information is a first value, a first bus coupled to the first master circuit, the second master circuit, and the first slave circuit, a bus controller is configured to transmit the access request signal to the first slave circuit via the first bus, a system controller directs the bus controller to substitute the first value for a second value on the identification information of the access request signal received from the second master circuit when the first master circuit is in the deactivated state.
摘要翻译：一种半导体集成电路，包括第一主电路，第二主电路，分配给第一主电路的第一从电路，并且当识别信息是第一值时，确定从第一主电路发送访问请求信号，耦合到第一主电路，第二主电路和第一从电路的第一总线，总线控制器被配置为经由第一总线将访问请求信号发送到第一从电路，系统控制器将总线控制器引导到当第一主电路处于去激活状态时，将从第二主电路接收的接入请求信号的识别信息替换第二值作为第二值。

89. 发明授权

US08612611B2 Proxy apparatus and operation method thereof 失效
标题翻译：代理设备及其操作方法
公开(公告)号：US08612611B2
公开(公告)日：2013-12-17
申请号：US13200820
申请日：2011-10-03
申请人： Masaharu Morimoto
发明人： Masaharu Morimoto
IPC分类号： G06F15/16
CPC分类号： H04L49/90 , H04L69/12
摘要： A proxy apparatus includes a multi-core CPU comprising a plurality of CPU cores; and an extended listen socket comprising a plurality of queues provided for the plurality of CPU cores respectively. A kernel thread and a proxy thread operate on each of the plurality of CPU cores. The kernel thread executes a receiving process of an establishment request packet of a first connection with a client terminal, assigned to a corresponding one of the plurality of CPU cores, and registers an establishment waiting socket which contained information of the first connection, on a corresponding one of the plurality of queues. The proxy thread refers to the corresponding queue, and establishes the first connection based on the establishment waiting socket when the establishment waiting socket is registered on the corresponding queue.
摘要翻译：代理装置包括：多核CPU，包括多个CPU核; 以及分别包括为多个CPU内核提供的多个队列的扩展监听套接字。内核线程和代理线程对多个CPU内核中的每一个进行操作。内核线程执行与分配给多个CPU核心中的相应一个CPU核心的客户机终端的第一次连接的建立请求分组的接收处理，并将包含第一连接的信息的建立等待套接字登记在相应的多个队列之一。代理线程是指相应的队列，并且当建立等待套接字注册在相应队列上时，基于建立等待套接字建立第一个连接。

90. 发明授权

US08607030B2 Scheduling threads instructions in variably selected or predetermined order periods of requested time ratio 有权
标题翻译：以所请求的时间比率可变地选择或预定的订单周期调度线程指令
公开(公告)号：US08607030B2
公开(公告)日：2013-12-10
申请号：US12585877
申请日：2009-09-28
申请人： Koji Adachi , Kazunori Miyamoto
发明人： Koji Adachi , Kazunori Miyamoto
IPC分类号： G06F9/38
CPC分类号： G06F9/3005 , G06F9/3851 , G06F9/4881 , G06F9/4893 , Y02D10/24
摘要： A multi-thread processor in accordance with an exemplary aspect of the present invention includes a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that outputs a thread selection signal TSEL designating a hardware thread to be executed in a next execution cycle, a first selector that outputs an instruction generated by a hardware thread selected according to the thread selection signal, and an execution pipeline that executes an instruction output from the first selector, wherein the thread scheduler specifies execution of at least one hardware thread selected in a fixed manner in a predetermined first execution period, and specifies execution of an arbitrary hardware thread in a second execution period.
摘要翻译：根据本发明的示例性方面的多线程处理器包括多个硬件线程，每个硬件线程生成独立的指令流程，线程调度器输出指定要在下一个执行的硬件线程的线程选择信号TSEL 执行周期，输出由根据所述线程选择信号选择的硬件线程生成的指令的第一选择器，以及执行从所述第一选择器输出的指令的执行流水线，其中所述线程调度器指定执行所选择的至少一个硬件线程以预定的第一执行周期中的固定方式，并且在第二执行周期中指定任意硬件线程的执行。

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