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81. 发明授权

US08341615B2 Single instruction multiple data (SIMD) code generation for parallel loops using versioning and scheduling 失效
标题翻译：使用版本控制和调度的并行循环的单指令多数据（SIMD）代码生成
公开(公告)号：US08341615B2
公开(公告)日：2012-12-25
申请号：US12172199
申请日：2008-07-11
申请人： Alexandre E. Eichenberger , Raul E. Silvera , Amy K. Wang , Guansong Zhang
发明人： Alexandre E. Eichenberger , Raul E. Silvera , Amy K. Wang , Guansong Zhang
IPC分类号： G06F9/45 , G06F9/46
CPC分类号： G06F8/456
摘要： Embodiments of the present invention address deficiencies of the art in respect to loop parallelization for a target architecture implementing a shared memory model and provide a novel and non-obvious method, system and computer program product for SIMD code generation for parallel loops using versioning and scheduling. In an embodiment of the invention, within a code compilation data processing system a parallel SIMD loop code generation method can include identifying a loop in a representation of source code as a parallel loop candidate, either through a user directive or through auto-parallelization. The method also can include selecting a trip count condition responsive to a scheduling policy set for the code compilation data processing system and also on a minimal simdizable threshold, determining a trip count and an alignment constraint for the selected loop, and generating a version of a parallel loop in the source code according to the alignment constraint and a comparison of the trip count to the trip count condition.
摘要翻译：本发明的实施例解决了实现共享存储器模型的目标架构的环路并行化方面的技术缺陷，并且提供了一种用于使用版本控制和调度的并行循环的SIMD代码生成的新颖且非显而易见的方法，系统和计算机程序产品。在本发明的一个实施例中，在代码编译数据处理系统中，并行SIMD循环码生成方法可以包括通过用户指令或通过自动并行化来将源代码表示中的循环识别为并行循环候选。该方法还可以包括响应于针对代码编译数据处理系统的调度策略集以及最小可仿真阈值来选择跳闸计数条件，确定所选循环的跳闸计数和对准约束，以及生成根据对齐约束在源代码中并行循环，并将行程计数与行程计数条件进行比较。

82. 发明申请

US20120290816A1 Optimized Scalar Promotion with Load and Splat SIMD Instructions 失效
标题翻译：通过加载和Splat SIMD指令优化标量升级
公开(公告)号：US20120290816A1
公开(公告)日：2012-11-15
申请号：US13555435
申请日：2012-07-23
申请人： Alexandre E. Eichenberger , Michael K. Gschwind , John A. Gunnels
发明人： Alexandre E. Eichenberger , Michael K. Gschwind , John A. Gunnels
IPC分类号： G06F9/30
CPC分类号： G06F8/45
摘要： Mechanisms for optimizing scalar code executed on a single instruction multiple data (SIMD) engine are provided. Placement of vector operation-splat operations may be determined based on an identification of scalar and SIMD operations in an original code representation. The original code representation may be modified to insert the vector operation-splat operations based on the determined placement of vector operation-splat operations to generate a first modified code representation. Placement of separate splat operations may be determined based on identification of scalar and SIMD operations in the first modified code representation. The first modified code representation may be modified to insert or delete separate splat operations based on the determined placement of the separate splat operations to generate a second modified code representation. SIMD code may be output based on the second modified code representation for execution by the SIMD engine.
摘要翻译：提供了在单指令多数据（SIMD）引擎上执行的优化标量代码的机制。可以基于原始代码表示中的标量和SIMD操作的标识来确定矢量操作 - 拼接操作的放置。可以修改原始代码表示以基于所确定的向量操作 - 分组操作的放置来插入向量操作 - 拼接操作以生成第一修改代码表示。可以基于第一修改代码表示中的标量和SIMD操作的标识来确定单独的拼接操作的放置。可以修改第一修改代码表示以基于确定的单独splat操作的布局来插入或删除单独的splat操作以生成第二修改代码表示。可以基于SIMD引擎执行的第二修改代码表示来输出SIMD代码。

83. 发明申请

US20120210073A1 WRITE-THROUGH CACHE OPTIMIZED FOR DEPENDENCE-FREE PARALLEL REGIONS 有权
标题翻译：写入 - 通过高速缓存优化为无依赖的并行区域
公开(公告)号：US20120210073A1
公开(公告)日：2012-08-16
申请号：US13025706
申请日：2011-02-11
申请人： Alexandre E. Eichenberger , Alan Gara , Martin Ohmacht , Vijayalakshmi Srinivasan
发明人： Alexandre E. Eichenberger , Alan Gara , Martin Ohmacht , Vijayalakshmi Srinivasan
IPC分类号： G06F12/08
CPC分类号： G06F12/0837
摘要： An apparatus, method and computer program product for improving performance of a parallel computing system. A first hardware local cache controller associated with a first local cache memory device of a first processor detects an occurrence of a false sharing of a first cache line by a second processor running the program code and allows the false sharing of the first cache line by the second processor. The false sharing of the first cache line occurs upon updating a first portion of the first cache line in the first local cache memory device by the first hardware local cache controller and subsequent updating a second portion of the first cache line in a second local cache memory device by a second hardware local cache controller.
摘要翻译：一种用于提高并行计算系统性能的装置，方法和计算机程序产品。与第一处理器的第一本地高速缓冲存储器设备相关联的第一硬件本地高速缓存控制器通过运行程序代码的第二处理器来检测第一高速缓存行的虚假共享的发生，并允许第一高速缓存行的错误共享由第二处理器。当由第一硬件本地高速缓存控制器更新第一本地高速缓存存储器设备中的第一高速缓存行的第一部分并且随后在第二本地高速缓冲存储器中更新第一高速缓存行的第二部分时，发生第一高速缓存行的错误共享设备由第二硬件本地缓存控制器。

84. 发明授权

US08156310B2 Method and apparatus for data stream alignment support 失效
标题翻译：数据流对齐支持的方法和装置
公开(公告)号：US08156310B2
公开(公告)日：2012-04-10
申请号：US11518692
申请日：2006-09-11
申请人： Alexandre E. Eichenberger , Michael Karl Gschwind , John-David Wellman , Peng Wu
发明人： Alexandre E. Eichenberger , Michael Karl Gschwind , John-David Wellman , Peng Wu
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F9/30032 , G06F9/30036
摘要： One embodiment of the present method and apparatus for data stream alignment support includes retrieving a first input from a first register file, retrieving a second input from a second register file, the second register file being dedicated to a stream shift unit and performing the stream shift instruction in accordance with the first input, the second input and a third input.
摘要翻译：用于数据流对准支持的本方法和装置的一个实施例包括从第一寄存器文件检索第一输入，从第二寄存器文件检索第二输入，第二寄存器文件专用于流移位单元并执行流移位指令根据第一输入，第二输入和第三输入。

85. 发明授权

US08146067B2 Efficient data reorganization to satisfy data alignment constraints 有权
标题翻译：有效的数据重组以满足数据对齐约束
公开(公告)号：US08146067B2
公开(公告)日：2012-03-27
申请号：US12108056
申请日：2008-04-23
申请人： Alexandre E. Eichenberger , John Kevin Patrick O'Brien , Peng Wu
发明人： Alexandre E. Eichenberger , John Kevin Patrick O'Brien , Peng Wu
IPC分类号： G06F9/45
CPC分类号： G06F8/4452
摘要： Vectorizing misaligned references in compiled code for SIMD architectures that support only aligned loads and stores is presented. In the framework presented herein, a loop is first simdized as if the memory unit imposes no alignment constraints. The compiler then inserts data reorganization operations to satisfy the actual alignment requirement of the hardware. Finally, the code generation algorithm generates SIMD codes based on the data reorganization graph, addressing realistic issues such as runtime alignments, unknown loop bounds, residue iteration counts, and multiple statements with arbitrary alignment combinations. Beyond generating a valid simdization, a preferred embodiment further improves the quality of the generated codes. Four stream-shift placement policies are disclosed, which minimize the number of data reorganization generated by the alignment handling.
摘要翻译：介绍了仅支持对齐加载和存储的SIMD架构的编译代码中的对齐引用。在本文提出的框架中，首先简化循环，就好像内存单元不会对齐约束。然后，编译器插入数据重组操作，以满足硬件的实际对齐要求。最后，代码生成算法基于数据重组图生成SIMD代码，解决诸如运行时对齐，未知循环边界，残差迭代计数以及具有任意对齐组合的多个语句之类的现实问题。除了生成有效的simdization之外，优选实施例进一步提高了生成代码的质量。公开了四个流移放置策略，其最小化由对齐处理产生的数据重组的数量。

86. 发明授权

US08136105B2 Method to exploit superword-level parallelism using semi-isomorphic packing 失效
标题翻译：利用半同构包装开发超级平行度的方法
公开(公告)号：US08136105B2
公开(公告)日：2012-03-13
申请号：US11536990
申请日：2006-09-29
申请人： Alexandre E. Eichenberger , Kai-Ting Amy Wang , Peng Wu , Peng Zhao
发明人： Alexandre E. Eichenberger , Kai-Ting Amy Wang , Peng Wu , Peng Zhao
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： A computer program product is provided for extracting SIMD parallelism. The computer program product includes instructions for providing a stream of input code comprising basic blocks; identifying pairs of statements that are semi-isomorphic with respect to each other within a basic block; iteratively combining into packs, pairs of statements that are semi-isomorphic with respect to each other, and combining packs into combined packs; collecting packs whose statements can be scheduled together for processing; and generating SIMD instructions for each pack to provide for extracting the SIMD parallelism..
摘要翻译：提供了一种用于提取SIMD并行性的计算机程序产品。计算机程序产品包括用于提供包括基本块的输入代码流的指令; 识别在基本块内相对于彼此半同构的语句对; 迭代地组合成包，相对于半同构的语句对，以及将包合并成组合包; 收集包，其陈述可以一起安排处理; 并为每个包生成SIMD指令以提供SIMD并行性。

87. 发明申请

US20120011348A1 Matrix Multiplication Operations Using Pair-Wise Load and Splat Operations 有权
标题翻译：使用配对加载和Splat操作的矩阵乘法运算
公开(公告)号：US20120011348A1
公开(公告)日：2012-01-12
申请号：US12834464
申请日：2010-07-12
申请人： Alexandre E. Eichenberger , Michael K. Gschwind , John A. Gunnels , Valentina Salapura
发明人： Alexandre E. Eichenberger , Michael K. Gschwind , John A. Gunnels , Valentina Salapura
IPC分类号： G06F9/302
CPC分类号： G06F9/30043 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/3887
摘要： Mechanisms for performing a matrix multiplication operation are provided. A vector load operation is performed to load a first vector operand of the matrix multiplication operation to a first target vector register. A pair-wise load and splat operation is performed to load a pair of scalar values of a second vector operand and replicate the pair of scalar values within a second target vector register. An operation is performed on elements of the first target vector register and elements of the second target vector register to generate a partial product of the matrix multiplication operation. The partial product is accumulated with other partial products and a resulting accumulated partial product is stored. This operation may be repeated for a second pair of scalar values of the second vector operand.
摘要翻译：提供了执行矩阵乘法运算的机构。执行向量加载操作以将矩阵乘法运算的第一向量操作数加载到第一目标向量寄存器。执行成对的加载和拼接操作以加载第二向量操作数的一对标量值，并在第二目标向量寄存器内复制一对标量值。对第一目标向量寄存器的元素和第二目标向量寄存器的元素执行操作，以生成矩阵乘法运算的部分乘积。部分产品与其他部分产品一起积累，并存储所得累积的部分产品。对于第二向量操作数的第二对标量值可以重复该操作。

88. 发明授权

US08087011B2 Domain stretching for an advanced dual-representation polyhedral loop transformation framework 失效
标题翻译：领域拉伸为先进的双重表示多面体环转换框架
公开(公告)号：US08087011B2
公开(公告)日：2011-12-27
申请号：US11861503
申请日：2007-09-26
申请人： Alexandre E. Eichenberger , John K. P. O'Brien , Kathryn M. O'Brien , Nicolas T. Vasilache
发明人： Alexandre E. Eichenberger , John K. P. O'Brien , Kathryn M. O'Brien , Nicolas T. Vasilache
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/452
摘要： Mechanisms for domain stretching for an advanced dual-representation polyhedral loop transformation framework are provided. The mechanisms of the illustrative embodiments address the weaknesses of the known polyhedral loop transformation based approaches by providing mechanisms for performing code generation transformations on individual statement instances in an intermediate representation generated by the polyhedral loop transformation optimization of the source code. These code generation transformations have the important property that they do not change program order of the statements in the intermediate representation. This property allows the result of the code generation transformations to be provided back to the polyhedral loop transformation mechanisms in a program statement view, via a new re-entrance path of the illustrative embodiments, for additional optimization. In addition, mechanisms are provided for stretching the domains of statements in a program loop view of the source code to thereby normalize the domains.
摘要翻译：提供了用于高级双重表示多面体环转换框架的域拉伸的机制。说明性实施例的机制通过提供用于在通过源代码的多面体环转换优化生成的中间表示中对各个语句实例执行代码生成变换的机制来解决已知的基于多面体循环变换的方法的弱点。这些代码生成转换具有重要的属性，它们不改变中间表示中的语句的程序顺序。该属性允许通过示例性实施例的新的重新导入路径将代码生成转换的结果提供给程序语句视图中的多面体循环变换机制，用于附加优化。另外，提供了用于在源代码的程序循环视图中拉伸语句的域的机制，从而使域标准化。

89. 发明申请

US20110314442A1 REDUCING PARALLELISM OF COMPUTER SOURCE CODE 有权
标题翻译：减少计算机源代码并行计算
公开(公告)号：US20110314442A1
公开(公告)日：2011-12-22
申请号：US12817999
申请日：2010-06-17
申请人： Uday Kumar Bondhugula , Alexandre E. Eichenberger , John Kevin P. O'Brien , Lakshminarayanan Renganarayana , Yuan Zhao
发明人： Uday Kumar Bondhugula , Alexandre E. Eichenberger , John Kevin P. O'Brien , Lakshminarayanan Renganarayana , Yuan Zhao
IPC分类号： G06F9/44
CPC分类号： G06F8/443 , G06F8/51
摘要： An example embodiment disclosed is a method for reducing parallelism of computer source code. The method includes receiving multi-threaded program source code and representing the multi-threaded program source code as a polyhedral framework stored in computer readable memory. The polyhedral framework is used to convert the polyhedral framework from the multi-threaded program source code representation to a single-threaded program source code representation.
摘要翻译：所公开的示例性实施例是用于减少计算机源代码的并行性的方法。该方法包括接收多线程程序源代码并将多线程程序源代码表示为存储在计算机可读存储器中的多面体框架。多面体框架用于将多面体框架从多线程程序源代码表示转换为单线程程序源代码表示。

90. 发明授权

US08056065B2 Stable transitions in the presence of conditionals for an advanced dual-representation polyhedral loop transformation framework 失效
标题翻译：在存在高级双重表示多面体循环转换框架的条件下的稳定转换
公开(公告)号：US08056065B2
公开(公告)日：2011-11-08
申请号：US11861512
申请日：2007-09-26
申请人： Alexandre E. Eichenberger , John K. P. O'Brien , Kathryn M. O'Brien , Nicolas T. Vasilache
发明人： Alexandre E. Eichenberger , John K. P. O'Brien , Kathryn M. O'Brien , Nicolas T. Vasilache
IPC分类号： G06F9/45
CPC分类号： G06F8/447
摘要： Mechanisms for stable transitions in the presence of conditionals for an advanced dual-representation polyhedral loop transformation framework are provided. The mechanisms of the illustrative embodiments address the weaknesses of the known polyhedral loop transformation based approaches by providing mechanisms for performing code generation transformations on individual statement instances in an intermediate representation generated by the polyhedral loop transformation optimization of the source code. These code generation transformations have the important property that they do not change program order of the statements in the intermediate representation. This property allows the result of the code generation transformations to be provided back to the polyhedral loop transformation mechanisms in a program statement view, via a new re-entrance path of the illustrative embodiments, for additional optimization. In addition, mechanisms are provided for ensuring code stabilization in the presence of conditions such that code bloat is not encountered during re-entrance.
摘要翻译：提供了在高级双重表示多面体环转换框架的条件下存在稳定转换的机制。说明性实施例的机制通过提供用于在通过源代码的多面体环转换优化生成的中间表示中对各个语句实例执行代码生成变换的机制来解决已知的基于多面体循环变换的方法的弱点。这些代码生成转换具有重要的属性，它们不改变中间表示中的语句的程序顺序。该属性允许通过示例性实施例的新的重新导入路径将代码生成转换的结果提供给程序语句视图中的多面体循环变换机制，用于附加优化。此外，还提供了在存在条件的情况下确保代码稳定的机制，使得在重入期间不会遇到代码膨胀。

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