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1. 发明申请

US20120210073A1 WRITE-THROUGH CACHE OPTIMIZED FOR DEPENDENCE-FREE PARALLEL REGIONS 有权
标题翻译：写入 - 通过高速缓存优化为无依赖的并行区域
公开(公告)号：US20120210073A1
公开(公告)日：2012-08-16
申请号：US13025706
申请日：2011-02-11
申请人： Alexandre E. Eichenberger , Alan Gara , Martin Ohmacht , Vijayalakshmi Srinivasan
发明人： Alexandre E. Eichenberger , Alan Gara , Martin Ohmacht , Vijayalakshmi Srinivasan
IPC分类号： G06F12/08
CPC分类号： G06F12/0837
摘要： An apparatus, method and computer program product for improving performance of a parallel computing system. A first hardware local cache controller associated with a first local cache memory device of a first processor detects an occurrence of a false sharing of a first cache line by a second processor running the program code and allows the false sharing of the first cache line by the second processor. The false sharing of the first cache line occurs upon updating a first portion of the first cache line in the first local cache memory device by the first hardware local cache controller and subsequent updating a second portion of the first cache line in a second local cache memory device by a second hardware local cache controller.
摘要翻译：一种用于提高并行计算系统性能的装置，方法和计算机程序产品。与第一处理器的第一本地高速缓冲存储器设备相关联的第一硬件本地高速缓存控制器通过运行程序代码的第二处理器来检测第一高速缓存行的虚假共享的发生，并允许第一高速缓存行的错误共享由第二处理器。当由第一硬件本地高速缓存控制器更新第一本地高速缓存存储器设备中的第一高速缓存行的第一部分并且随后在第二本地高速缓冲存储器中更新第一高速缓存行的第二部分时，发生第一高速缓存行的错误共享设备由第二硬件本地缓存控制器。

2. 发明申请

US20120331232A1 WRITE-THROUGH CACHE OPTIMIZED FOR DEPENDENCE-FREE PARALLEL REGIONS 有权
标题翻译：写入 - 通过高速缓存优化为无依赖的并行区域
公开(公告)号：US20120331232A1
公开(公告)日：2012-12-27
申请号：US13604349
申请日：2012-09-05
申请人： Alexandre E. Eichenberger , Alan Gara , Martin Ohmacht , Vijayalakshmi Srinivasan
发明人： Alexandre E. Eichenberger , Alan Gara , Martin Ohmacht , Vijayalakshmi Srinivasan
IPC分类号： G06F12/08
CPC分类号： G06F12/0837
摘要： An apparatus and computer program product for improving performance of a parallel computing system. A first hardware local cache controller associated with a first local cache memory device of a first processor detects an occurrence of a false sharing of a first cache line by a second processor running the program code and allows the false sharing of the first cache line by the second processor. The false sharing of the first cache line occurs upon updating a first portion of the first cache line in the first local cache memory device by the first hardware local cache controller and subsequent updating a second portion of the first cache line in a second local cache memory device by a second hardware local cache controller.
摘要翻译：一种用于提高并行计算系统性能的设备和计算机程序产品。与第一处理器的第一本地高速缓冲存储器设备相关联的第一硬件本地高速缓存控制器通过运行程序代码的第二处理器来检测第一高速缓存行的虚假共享的发生，并允许第一高速缓存行的错误共享由第二处理器。当由第一硬件本地高速缓存控制器更新第一本地高速缓存存储器设备中的第一高速缓存行的第一部分并且随后在第二本地高速缓冲存储器中更新第一高速缓存行的第二部分时，发生第一高速缓存行的错误共享设备由第二硬件本地缓存控制器。

3. 发明申请

US20110047334A1 Checkpointing in Speculative Versioning Caches 失效
标题翻译：推测版本控制缓存中的检查点
公开(公告)号：US20110047334A1
公开(公告)日：2011-02-24
申请号：US12544704
申请日：2009-08-20
申请人： Alexandre E. Eichenberger , Alan Gara , Michael K. Gschwind , Martin Ohmacht
发明人： Alexandre E. Eichenberger , Alan Gara , Michael K. Gschwind , Martin Ohmacht
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0842 , G06F11/1405
摘要： Mechanisms for generating checkpoints in a speculative versioning cache of a data processing system are provided. The mechanisms execute code within the data processing system, wherein the code accesses cache lines in the speculative versioning cache. The mechanisms further determine whether a first condition occurs indicating a need to generate a checkpoint in the speculative versioning cache. The checkpoint is a speculative cache line which is made non-speculative in response to a second condition occurring that requires a roll-back of changes to a cache line corresponding to the speculative cache line. The mechanisms also generate the checkpoint in the speculative versioning cache in response to a determination that the first condition has occurred.
摘要翻译：提供了用于在数据处理系统的推测版本缓存中生成检查点的机制。这些机制在数据处理系统内执行代码，其中代码访问推测版本控制缓存中的高速缓存行。这些机制进一步确定是否出现指示在推测版本控制高速缓存中生成检查点的需要的第一条件。检查点是推测性高速缓存行，其响应于需要向对应于推测性高速缓存行的高速缓存行的回滚而返回的第二条件而变得不推测。这些机制还响应于确定第一个条件已经发生，在推测版本控制缓存中生成检查点。

4. 发明授权

US08397052B2 Version pressure feedback mechanisms for speculative versioning caches 失效
标题翻译：针对推测版本控制缓存的版本压力反馈机制
公开(公告)号：US08397052B2
公开(公告)日：2013-03-12
申请号：US12543688
申请日：2009-08-19
申请人： Alexandre E. Eichenberger , Alan Gara , Kathryn M. O'Brien , Martin Ohmacht , Xiaotong Zhuang
发明人： Alexandre E. Eichenberger , Alan Gara , Kathryn M. O'Brien , Martin Ohmacht , Xiaotong Zhuang
IPC分类号： G06F9/318
CPC分类号： G06F9/3851 , G06F9/3885 , G06F12/0842
摘要： Mechanisms are provided for controlling version pressure on a speculative versioning cache. Raw version pressure data is collected based on one or more threads accessing cache lines of the speculative versioning cache. One or more statistical measures of version pressure are generated based on the collected raw version pressure data. A determination is made as to whether one or more modifications to an operation of a data processing system are to be performed based on the one or more statistical measures of version pressure, the one or more modifications affecting version pressure exerted on the speculative versioning cache. An operation of the data processing system is modified based on the one or more determined modifications, in response to a determination that one or more modifications to the operation of the data processing system are to be performed, to affect the version pressure exerted on the speculative versioning cache.
摘要翻译：提供了用于控制推测版本缓存的版本压力的机制。基于访问推测性版本缓存的高速缓存行的一个或多个线程来收集原始版本压力数据。基于收集的原始版本压力数据生成版本压力的一个或多个统计度量。确定是否将基于版本压力的一个或多个统计测量来执行对数据处理系统的操作的一个或多个修改，该一个或多个修改影响施加在推测版本缓存上的版本压力。响应于将要执行对数据处理系统的操作的一个或多个修改以影响施加在投机上的版本压力的确定，基于一个或多个确定的修改来修改数据处理系统的操作版本缓存。

5. 发明授权

US09081501B2 Multi-petascale highly efficient parallel supercomputer 有权
标题翻译：多千兆高效并行超级计算机
公开(公告)号：US09081501B2
公开(公告)日：2015-07-14
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/173 , G06F9/06 , G06F15/76
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

6. 发明申请

US20110219208A1 MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER 有权
标题翻译：多层高效平行超级计算机
公开(公告)号：US20110219208A1
公开(公告)日：2011-09-08
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

7. 发明申请

US20110047362A1 Version Pressure Feedback Mechanisms for Speculative Versioning Caches 失效
标题翻译：版本控制缓存的版本压力反馈机制
公开(公告)号：US20110047362A1
公开(公告)日：2011-02-24
申请号：US12543688
申请日：2009-08-19
申请人： Alexandre E. Eichenberger , Alan Gara , Kathryn M. O'Brien , Martin Ohmacht , Xiaotong Zhuang
发明人： Alexandre E. Eichenberger , Alan Gara , Kathryn M. O'Brien , Martin Ohmacht , Xiaotong Zhuang
IPC分类号： G06F12/08 , G06F9/318
CPC分类号： G06F9/3851 , G06F9/3885 , G06F12/0842
摘要： Mechanisms are provided for controlling version pressure on a speculative versioning cache. Raw version pressure data is collected based on one or more threads accessing cache lines of the speculative versioning cache. One or more statistical measures of version pressure are generated based on the collected raw version pressure data. A determination is made as to whether one or more modifications to an operation of a data processing system are to be performed based on the one or more statistical measures of version pressure, the one or more modifications affecting version pressure exerted on the speculative versioning cache. An operation of the data processing system is modified based on the one or more determined modifications, in response to a determination that one or more modifications to the operation of the data processing system are to be performed, to affect the version pressure exerted on the speculative versioning cache.
摘要翻译：提供了用于控制推测版本缓存的版本压力的机制。基于访问推测性版本缓存的高速缓存行的一个或多个线程来收集原始版本压力数据。基于收集的原始版本压力数据生成版本压力的一个或多个统计度量。确定是否将基于版本压力的一个或多个统计测量来执行对数据处理系统的操作的一个或多个修改，该一个或多个修改影响施加在推测版本缓存上的版本压力。响应于将要执行对数据处理系统的操作的一个或多个修改以影响施加在投机上的版本压力的确定，基于一个或多个确定的修改来修改数据处理系统的操作版本缓存。

8. 发明授权

US08521961B2 Checkpointing in speculative versioning caches 失效
标题翻译：在投机版本控制缓存中进行检查点
公开(公告)号：US08521961B2
公开(公告)日：2013-08-27
申请号：US12544704
申请日：2009-08-20
申请人： Alexandre E. Eichenberger , Alan Gara , Michael K. Gschwind , Martin Ohmacht
发明人： Alexandre E. Eichenberger , Alan Gara , Michael K. Gschwind , Martin Ohmacht
IPC分类号： G06F12/00
CPC分类号： G06F12/0842 , G06F11/1405
摘要： Mechanisms for generating checkpoints in a speculative versioning cache of a data processing system are provided. The mechanisms execute code within the data processing system, wherein the code accesses cache lines in the speculative versioning cache. The mechanisms further determine whether a first condition occurs indicating a need to generate a checkpoint in the speculative versioning cache. The checkpoint is a speculative cache line which is made non-speculative in response to a second condition occurring that requires a roll-back of changes to a cache line corresponding to the speculative cache line. The mechanisms also generate the checkpoint in the speculative versioning cache in response to a determination that the first condition has occurred.
摘要翻译：提供了用于在数据处理系统的推测版本缓存中生成检查点的机制。这些机制在数据处理系统内执行代码，其中代码访问推测版本控制缓存中的高速缓存行。这些机制进一步确定是否出现指示在推测版本控制高速缓存中生成检查点的需要的第一条件。检查点是推测性高速缓存行，其响应于需要向对应于推测性高速缓存行的高速缓存行的回滚而返回的第二条件而变得不推测。这些机制还响应于确定第一个条件已经发生，在推测版本控制缓存中生成检查点。

9. 发明授权

US08458684B2 Insertion of operation-and-indicate instructions for optimized SIMD code 有权
标题翻译：插入优化SIMD代码的操作和指示说明
公开(公告)号：US08458684B2
公开(公告)日：2013-06-04
申请号：US12543628
申请日：2009-08-19
申请人： Alexandre E. Eichenberger , Alan Gara , Michael K. Gschwind
发明人： Alexandre E. Eichenberger , Alan Gara , Michael K. Gschwind
IPC分类号： G06F9/45
CPC分类号： G06F8/451 , G06F9/30036 , G06F9/30043 , G06F9/3865 , G06F9/3887
摘要： Mechanisms are provided for inserting indicated instructions for tracking and indicating exceptions in the execution of vectorized code. A portion of first code is received for compilation. The portion of first code is analyzed to identify non-speculative instructions performing designated non-speculative operations in the first code that are candidates for replacement by replacement operation-and-indicate instructions that perform the designated non-speculative operations and further perform an indication operation for indicating any exception conditions corresponding to special exception values present in vector register inputs to the replacement operation-and-indicate instructions. The replacement is performed and second code is generated based on the replacement of the at least one non-speculative instruction. The data processing system executing the compiled code is configured to store special exception values in vector output registers, in response to a speculative instruction generating an exception condition, without initiating exception handling.
摘要翻译：提供了用于在执行向量化代码中插入指示的跟踪指示和指示异常的机制。第一个代码的一部分被接收用于编译。对第一代码的部分进行分析，以识别在第一代码中执行指定的非推测操作的非推测指令，该第一代码中的替代操作指示指令执行指定的非投机操作并进一步执行指示操作用于指示对应于向量寄存器输入中存在的替换操作和指示指令的特殊异常值的任何异常条件。执行替换，并且基于替换至少一个非推测性指令来生成第二代码。执行编译代码的数据处理系统被配置为在矢量输出寄存器中存储特殊异常值，以响应于产生异常条件的推测指令，而不启动异常处理。

10. 发明申请

US20110047358A1 In-Data Path Tracking of Floating Point Exceptions and Store-Based Exception Indication 审中-公开
标题翻译：浮点异常和基于存储的异常指示的数据间路径跟踪
公开(公告)号：US20110047358A1
公开(公告)日：2011-02-24
申请号：US12543614
申请日：2009-08-19
申请人： Alexandre E. Eichenberger , Alan Gara , Michael K. Gschwind
发明人： Alexandre E. Eichenberger , Alan Gara , Michael K. Gschwind
IPC分类号： G06F9/30 , G06F9/302
CPC分类号： G06F9/30018 , G06F9/30021 , G06F9/30029 , G06F9/30036 , G06F9/3013 , G06F9/3842 , G06F9/3865
摘要： Mechanisms are provided for tracking exceptions in the execution of vectorized code. A speculative instruction is executed on a vector element of a vector. An exception condition is detected in association with the vector element based on a result of executing the speculative instruction on the vector element. A special exception value is stored in the vector element in a vector register corresponding to the vector, indicative of the exception condition, without invoking an exception handler for the exception condition. The special exception value is propagated with the vector element of the vector through a processor architecture of the processor, without invoking the exception handler for the exception condition. An exception corresponding to the exception condition indicated by the special exception value is generated only in response to a non-speculative instruction being executed that performs a non-speculative operation on the vector element.
摘要翻译：提供了用于跟踪执行向量化代码中的异常的机制。对向量的向量元素执行推测指令。基于向量元素执行推测指令的结果，与向量元素相关联地检测异常条件。一个特殊的异常值被存储在矢量寄存器的向量寄存器中，该向量寄存器对应于向量，表示异常条件，而不调用异常条件的异常处理程序。特殊异常值通过处理器的处理器架构与向量的向量元素传播，而不调用异常条件的异常处理程序。由特殊异常值指示的异常条件对应的异常仅在响应于执行对向量元素执行非推测性操作的非推测性指令时产生。

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