专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US06660619B1 Dual damascene metal interconnect structure with dielectric studs 失效
标题翻译：双镶嵌金属互连结构与介质螺柱
公开(公告)号：US06660619B1
公开(公告)日：2003-12-09
申请号：US10058048
申请日：2002-01-29
申请人： Suzette K. Pangrle , Lynne A. Okada , Fei Wang
发明人： Suzette K. Pangrle , Lynne A. Okada , Fei Wang
IPC分类号： H01L213205
CPC分类号： H01L21/76835 , H01L21/76808 , H01L2221/1026
摘要： A method for forming a dual damascene conductive line and conductive plug using porous low k dielectric materials in the via and trench layers. The via layer is provided with dense low k dielectric plugs that increase the mechanical strength of the porous low k dielectric layer that forms the via layer. A via fill technique etches some of the dielectric plugs in the via layer and fills them with conductive material. The via fill technique reduces the damage done to the via holes in the via layer caused by photoresist removal processes.
摘要翻译：一种用于在通孔和沟槽层中使用多孔低k介电材料形成双镶嵌导电线和导电塞的方法。通孔层设置有致密的低k电介质塞，其增加形成通孔层的多孔低k电介质层的机械强度。通孔填充技术蚀刻通孔层中的一些电介质塞，并用导电材料填充它们。通孔填充技术减少了由光致抗蚀剂去除工艺引起的通孔中通孔的损伤。

82. 发明授权

US06610608B1 Plasma etching using combination of CHF3 and CH3F 有权
标题翻译：使用CHF3和CH3F的组合进行等离子体蚀刻
公开(公告)号：US06610608B1
公开(公告)日：2003-08-26
申请号：US09809300
申请日：2001-03-16
申请人： Lynne A. Okada , Fei Wang , Calvin T. Gabriel
发明人： Lynne A. Okada , Fei Wang , Calvin T. Gabriel
IPC分类号： H01L21302
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/76829
摘要： A method of manufacturing a semiconductor device includes forming a first level, forming a first barrier layer over the first level, forming a dielectric layer over the first barrier layer, forming an opening through the dielectric layer, etching the first barrier layer, and filling the opening with metal to form a first metal feature. The first barrier level is etched using CHF3 and CH3F. Additionally, the first barrier layer can be formed from silicon nitride.
摘要翻译：一种制造半导体器件的方法包括形成第一层，在第一层上形成第一势垒层，在第一势垒层上形成电介质层，形成通过电介质层的开口，蚀刻第一阻挡层，并填充用金属打开以形成第一金属特征。使用CHF3和CH3F蚀刻第一个阻挡层。另外，第一阻挡层可以由氮化硅形成。

83. 发明授权

US06599839B1 Plasma etch process for nonhomogenous film 有权
标题翻译：非均匀膜的等离子体蚀刻工艺
公开(公告)号：US06599839B1
公开(公告)日：2003-07-29
申请号：US09773906
申请日：2001-02-02
申请人： Calvin T. Gabriel , Lynne A. Okada , Dawn M. Hopper , Suzette K. Pangrle , Fei Wang
发明人： Calvin T. Gabriel , Lynne A. Okada , Dawn M. Hopper , Suzette K. Pangrle , Fei Wang
IPC分类号： H01L21302
CPC分类号： H01L21/31138 , C23F1/12 , H01L21/31116 , H01L21/31144 , H01L21/76802
摘要： A composite layer comprising a non-homogenous layer is etched by continuously varying a process parameter, such as the amount of reactive agent in an etchant mixture. Embodiments include etching a silicon oxide film having a varying concentration of carbon through the film with an etchant mixture containing a fluorinated organic, oxygen and an inert gas and continuously increasing and/or decreasing the amount of oxygen in the etchant mixture during etching through the silicon oxide film.
摘要翻译：通过连续改变工艺参数（例如蚀刻剂混合物中的反应剂的量）蚀刻包含非均匀层的复合层。实施例包括用含有氟化有机物，氧气和惰性气体的蚀刻剂混合物蚀刻具有不同浓度碳的氧化硅膜，并且在通过硅蚀刻过程中连续增加和/或减少蚀刻剂混合物中的氧气量氧化膜。

84. 发明授权

US06583046B1 Post-treatment of low-k dielectric for prevention of photoresist poisoning 有权
标题翻译：用于防止光致抗蚀剂中毒的低k电介质的后处理
公开(公告)号：US06583046B1
公开(公告)日：2003-06-24
申请号：US09903757
申请日：2001-07-13
申请人： Lynne A. Okada , Fei Wang , Calvin T. Gabriel
发明人： Lynne A. Okada , Fei Wang , Calvin T. Gabriel
IPC分类号： H01L214763
CPC分类号： H01L21/76826 , H01L21/02063 , H01L21/31138 , H01L21/76807
摘要： Deleterious poisoning of patterned photoresist masking layers accompanying plasma ashing/etching of photoresist and/or low-k dielectric layers in a nitrogen-containing atmosphere is eliminated, or at least substantially reduced, by post-treating exposed surfaces of the low-k dielectric layer(s) with hydrogen, e.g. by contact with H2 gas at an elevated temperature or with a H2 plasma subsequent to plasma ashing/etching. The invention enjoys particular utility in the formation of dual damascene openings in dielectric layers as part of metallization processing of semiconductor IC devices.
摘要翻译：通过对低k电介质层的暴露表面进行后处理，消除或至少大大减少伴随着含氮气氛中的光致抗蚀剂和/或低k电介质层的等离子体灰化/蚀刻的图案化光刻胶掩模层的有害中毒（例如）通过在升高的温度下与H 2气体接触或者在等离子体灰化/蚀刻之后与H 2等离子体接触。本发明在形成作为半导体IC器件的金属化处理的一部分的电介质层中的双镶嵌开口中具有特别的用途。

85. 发明授权

US06541871B2 Method for fabricating a stacked chip package 有权
公开(公告)号：US06541871B2
公开(公告)日：2003-04-01
申请号：US10098516
申请日：2002-03-18
申请人： Tsung-Ming Pai , Chung-Hao Lee , Pao-Hei Chang Chin , Meng-Hui Lin , Song-Fei Wang
发明人： Tsung-Ming Pai , Chung-Hao Lee , Pao-Hei Chang Chin , Meng-Hui Lin , Song-Fei Wang
IPC分类号： H01L2348
CPC分类号： H01L25/50 , H01L24/73 , H01L25/0657 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83856 , H01L2224/92247 , H01L2225/0651 , H01L2924/01087 , H01L2924/15311 , H01L2924/3511 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A method for fabricating a stacked chip package comprises the steps of: (a) attaching a first semiconductor chip to an upper surface of a substrate through a first adhesive layer; (b) partially curing the first adhesive layer such that it gels but does not harden; (c) attaching a second semiconductor chip to the first semiconductor chip through a second adhesive layer; (d) curing the first and second adhesive layer; (e) electrically coupling the first and second semiconductor chips to a structure for making external electrical connection provided on the substrate; and (f) forming a package body over the first semiconductor chip, the second semiconductor chip, and a portion of the upper surface of the substrate. Since the first and second adhesive layers may be cured in one single step, the cycle time may be reduced thereby cutting down the production cost.

86. 发明授权

US06475929B1 Method of manufacturing a semiconductor structure with treatment to sacrificial stop layer producing diffusion to an adjacent low-k dielectric layer lowering the constant 有权
标题翻译：制造具有牺牲停止层处理的半导体结构的方法，其产生扩散到相邻的低k电介质层，从而降低常数
公开(公告)号：US06475929B1
公开(公告)日：2002-11-05
申请号：US09774708
申请日：2001-02-01
申请人： Calvin T. Gabriel , Suzette K. Pangrle , Lynne A. Okada , Fei Wang
发明人： Calvin T. Gabriel , Suzette K. Pangrle , Lynne A. Okada , Fei Wang
IPC分类号： H01L2358
CPC分类号： H01L21/76829 , H01L21/7681 , H01L21/76825 , H01L21/76828 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a low-k semiconductor structure including the steps of forming a low-k dielectric layer, forming a sacrificial etch stop layer adjacent the low-k dielectric layer, and applying energy to the sacrificial etch stop layer to diffuse a component of the sacrificial etch stop layer into the adjacent low-k dielectric layer. This diffusion of the component lowers the dielectric constant of the adjacent low-k dielectric layer.
摘要翻译：一种制造低k半导体结构的方法，包括以下步骤：形成低k电介质层，形成与低k电介质层相邻的牺牲蚀刻停止层，以及向牺牲蚀刻停止层施加能量以扩散部分牺牲蚀刻停止层进入相邻的低k电介质层。组件的这种扩散降低了相邻低k电介质层的介电常数。

87. 发明授权

US06465343B1 Method for forming backend interconnect with copper etching and ultra low-k dielectric materials 失效
标题翻译：用铜蚀刻和超低k电介质材料形成后端互连的方法
公开(公告)号：US06465343B1
公开(公告)日：2002-10-15
申请号：US09793986
申请日：2001-02-28
申请人： Fei Wang
发明人： Fei Wang
IPC分类号： H01L214763
CPC分类号： H01L21/76819 , H01L21/31144 , H01L21/32139 , H01L21/76802 , H01L21/76885
摘要： A method for forming a metal interconnect structure provides a copper conductive layer which is etched to form conductive lines. A low k dielectric material is provided in the spaces formed between the copper lines. Since any photoresist material that was previously used in forming the copper lines is removed prior to the deposition of the low k dielectric materials between the lines, this low k dielectric layer is not subjected to a photoresist removal process. Sidewall damage low k dielectric material is thereby avoided so that line-to-line capacitance in the metal interconnect structure is not compromised.
摘要翻译：形成金属互连结构的方法提供了铜导电层，其被蚀刻以形成导电线。在铜线之间形成的空间中提供低k电介质材料。由于先前用于形成铜线的任何光致抗蚀剂材料在两条线之间沉积低k介电材料之前被去除，所以该低k电介质层不经受光致抗蚀剂去除工艺。从而避免侧壁损坏低k电介质材料，从而不会损害金属互连结构中的线间电容。

88. 发明授权

US06444573B1 Method of making a slot via filled dual damascene structure with a middle stop layer 有权
标题翻译：通过具有中间停止层的填充双镶嵌结构制造槽的方法
公开(公告)号：US06444573B1
公开(公告)日：2002-09-03
申请号：US09788472
申请日：2001-02-21
申请人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , Calvin T. Gabriel
发明人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , Calvin T. Gabriel
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76808 , Y10S977/888
摘要： An interconnect structure and method of forming the same in which a first inorganic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric layer are etched to form a slot via in the first dielectric layer. The slot via is longer than the width of a subsequently formed trench. A second low k dielectric material is deposited within the slot via and over the etch stop layer, to form a second dielectric layer over the slot via and the etch stop layer. The re-filled slot via is simultaneously etched with the second dielectric layer in which a trench is formed. The entire width of the trench is over the via that is etched. The re-opened via and the trench are filled with a conductive material.
摘要翻译：一种互连结构及其形成方法，其中第一无机低k电介质材料沉积在导电层上以形成第一介电层。在第一电介质层上形成蚀刻停止层。蚀刻停止层和第一介电层被蚀刻以在第一介电层中形成槽通孔。狭缝通孔比随后形成的沟槽的宽度长。第二低k电介质材料通过蚀刻停止层上方和上方沉积在槽内，以在槽通孔和蚀刻停止层上形成第二电介质层。再填充的槽通孔与其中形成沟槽的第二电介质层同时蚀刻。沟槽的整个宽度在被蚀刻的通孔之上。重新打开的通孔和沟槽填充有导电材料。

89. 发明授权

US06424039B1 Dual damascene process using sacrificial spin-on materials 有权
公开(公告)号：US06424039B1
公开(公告)日：2002-07-23
申请号：US09532731
申请日：2000-03-22
申请人： Fei Wang , Bhanwar Singh , James K. Kai
发明人： Fei Wang , Bhanwar Singh , James K. Kai
IPC分类号： H01L2348
摘要： A dual damascene process includes the steps of forming a contact hole in an oxide layer disposed above a semiconductor substrate, disposing a layer of anti-reflective coating material on top of the oxide layer and in the contact hole, and partially etching the layer of anti-reflective coating material and the oxide layer to form the wiring trough. The partial etching step includes the steps of spin coating photoresist on top of the anti-reflective coating material, exposing the photoresist through a mask containing a pattern of the wiring trough, developing the photoresist to expose portions of the anti-reflective coating material, dry etching the exposed portions of the anti-reflective coating material to expose portions of the oxide layer, and wet etching the exposed portions of the oxide layer to form the wiring trough.

90. 发明授权

US06420752B1 Semiconductor device with self-aligned contacts using a liner oxide layer 有权
标题翻译：具有使用衬垫氧化物层的自对准触点的半导体器件
公开(公告)号：US06420752B1
公开(公告)日：2002-07-16
申请号：US09502163
申请日：2000-02-11
申请人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
发明人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L21/76829 , H01L21/76897 , H01L27/115 , H01L2924/3011
摘要： A semiconductor device for minimizing auto-doping problems is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.
摘要翻译：公开了一种用于最小化自动掺杂问题的半导体器件。蚀刻停止层被消除并且被可消耗的衬垫氧化物层代替，使得该器件的层叠栅极结构可以被更靠近地放置在一起，从而允许器件收缩。衬垫氧化物层直接形成在衬底上并且与堆叠的栅极结构，侧壁间隔物以及形成在衬底上的源极和漏极接触并且用作介电层的自动掺杂势垒，以防止形成在衬底中的硼和磷电介质层自动掺入源和漏极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式