专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明申请

US20090020855A1 METHOD FOR STACKING SERIALLY-CONNECTED INTEGRATED CIRCUITS AND MULTI-CHIP DEVICE MADE FROM SAME 有权
标题翻译：用于堆叠串联集成电路的方法和从其生成的多芯片器件
公开(公告)号：US20090020855A1
公开(公告)日：2009-01-22
申请号：US12236874
申请日：2008-09-24
申请人： Hong Beom PYEON
发明人： Hong Beom PYEON
IPC分类号： H01L21/60 , H01L23/538
CPC分类号： H01L25/0657 , G11C5/02 , G11C5/066 , G11C16/06 , G11C19/00 , H01L21/76898 , H01L24/06 , H01L2224/05554 , H01L2225/06513 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01057 , H01L2924/01058 , H01L2924/01079 , H01L2924/01082 , H01L2924/10329 , H01L2924/14 , H01L2924/00
摘要： A multi-chip device and method of stacking a plurality substantially identical chips to produce the device are provided. The multi-chip device, or circuit, includes at least one through-chip via providing a parallel connection between signal pads from at least two chips, and at least one through-chip via providing a serial or daisy chain connection between signal pads from at least two chips. Common connection signal pads are arranged symmetrically about a center line of the chip with respect to duplicate common signal pads. Input signal pads are symmetrically disposed about the center line of the chip with respect to corresponding output signal pads. The chips in the stack are alternating flipped versions of the substantially identical chip to provide for this arrangement. At least one serial connection is provided between signal pads of stacked and flipped chips when more than two chips are stacked.
摘要翻译：提供了堆叠多个基本上相同的芯片以产生该装置的多芯片装置和方法。多芯片器件或电路包括至少一个穿芯片通孔，其通过提供来自至少两个芯片的信号焊盘之间的并联连接以及至少一个穿芯片通孔，以提供从信号焊盘处的串联或菊花链连接至少两块芯片。公共连接信号焊盘相对于重复的公共信号焊盘对称地布置在芯片的中心线上。输入信号焊盘相对于相应的输出信号焊盘对称地设置在芯片的中心线周围。堆叠中的芯片是基本上相同的芯片的交替翻转版本，以提供这种布置。当堆叠超过两个芯片时，至少有一个串行连接提供在堆叠和翻转芯片的信号焊盘之间。

82. 发明申请

US20080198682A1 SEMICONDUCTOR DEVICE AND METHOD FOR SELECTION AND DE-SELECTION OF MEMORY DEVICES INTERCONNECTED IN SERIES 失效
标题翻译：用于选择和选择系列中互连的存储器件的半导体器件和方法
公开(公告)号：US20080198682A1
公开(公告)日：2008-08-21
申请号：US12025866
申请日：2008-02-05
申请人： Hong Beom PYEON
发明人： Hong Beom PYEON
IPC分类号： G11C8/10
CPC分类号： G11C19/00
摘要： A system includes a plurality of memory devices connected in-series that communicate with a memory controller. When a memory device receives a command strobe signal indicating the start of a command having an ID number, the memory device is placed in a de-selected state and the ID number is compared to the memory device's device address. Delayed versions of the command strobe signal and the command are forwarded while the memory device is in the de-selected state. If the ID number matches the device address with reference to the ID number, the memory device is placed in a selected state. In the selected state, the memory device may refrain from forwarding the delayed versions of the command strobe signal and the command, such that if there is a match, a truncated part of the command is forwarded before the memory device is placed in the selected state.
摘要翻译：系统包括与存储器控制器通信的串联连接的多个存储器件。当存储器装置接收到指示具有ID号的命令的开始的命令选通信号时，将存储器件置于取消选择状态，并将ID号与存储器件的器件地址进行比较。当存储器件处于取消选择状态时，命令选通信号和命令的延迟版本被转发。如果ID编号与设备地址相匹配，则将存储设备置于选择状态。在选择状态下，存储装置可以避免转发命令选通信号和命令的延迟版本，使得如果存在匹配，则在将存储装置置于选择状态之前转发命令的截断部分。

83. 发明申请

US20080192649A1 APPARATUS AND METHOD FOR PRODUCING IDENTIFIERS REGARDLESS OF MIXED DEVICE TYPE IN A SERIAL INTERCONNECTION 有权
标题翻译：用于生产符合串行互连的混合器件类型的标识符的装置和方法
公开(公告)号：US20080192649A1
公开(公告)日：2008-08-14
申请号：US11692446
申请日：2007-03-28
申请人： Hong Beom PYEON , HakJune OH , Jin-Ki KIM , Shuji SUMI
发明人： Hong Beom PYEON , HakJune OH , Jin-Ki KIM , Shuji SUMI
IPC分类号： H04L12/28
CPC分类号： G11C7/1078 , G11C7/1051 , G11C7/1063 , G11C7/109
摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) is serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID accompanying the fed DT for another device and the fed ID is latched in a register of the device. In a case of no match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. With reference to device type provided to the interconnected devices, IDs are sequentially generated. The SI containing the DT, the ID and an ID generation command is transmitted in a packet basis to a next device. A memory controller can recognize the total number of one DT, in response to the ID received from the last device. In a case of a “don't care” DT is provided to the interconnected devices, IDs are sequentially generated and the total number of the interconnected devices is recognized, regardless of the differences in DTs of the devices.
摘要翻译：混合型的多个存储器件（例如，DRAM，SRAM，MRAM以及NAND，NOR和AND型闪存）被串联连接。每个设备都有其设备类型的设备类型信息。作为分组的串行输入（SI）中包含的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。设备确定馈送的DT是否匹配设备的DT。在匹配的情况下，包括在设备中的计算器执行计算以生成伴随用于另一设备的馈送DT的ID，并且将馈送的ID锁存在设备的寄存器中。在不匹配的情况下，跳过ID生成，并且不会为其他设备生成ID。根据设备类型匹配确定，DT与所生成或接收的ID组合。组合的DT和ID作为传送到下一个设备的分组。在串行互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。参考提供给互连设备的设备类型，依次生成ID。将包含DT，ID和ID生成命令的SI以分组的形式发送到下一个设备。响应于从最后一个设备接收的ID，存储器控制器可以识别一个DT的总数。在“不关心”的情况下，将DT提供给互连设备，不管设备的DT的差异如何，顺序地生成ID并且识别互连设备的总数。

84. 发明申请

US20080181214A1 APPARATUS AND METHOD FOR PRODUCING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES OF MIXED TYPE 有权
标题翻译：用于生产混合类型的串联互连设备的设备标识符的装置和方法
公开(公告)号：US20080181214A1
公开(公告)日：2008-07-31
申请号：US11692452
申请日：2007-03-28
申请人： Hong Beom Pyeon , HakJune Oh , Jin-Ki Kim , Shuji Sumi
发明人： Hong Beom Pyeon , HakJune Oh , Jin-Ki Kim , Shuji Sumi
IPC分类号： H04L12/56
CPC分类号： G06F13/4243
摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. In a case of no-match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the several interconnection. With reference to device type provided to the interconnected devices, IDs are sequentially generated. The SI containing the DT, the ID and an ID generation command is transmitted in a packet basis to a next device.
摘要翻译：多个混合型存储器件（例如，DRAM，SRAM，MRAM以及NAND-，NOR-和AND-型闪存）被串联连接。每个设备都有其设备类型的设备类型信息。作为分组的串行输入（SI）中包含的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。设备确定馈送的DT是否匹配设备的DT。在匹配的情况下，包含在该设备中的计算器执行计算以生成另一设备的ID，并且将馈送的ID锁存在设备的寄存器中。在不匹配的情况下，跳过ID生成，并且不为另一设备生成ID。根据设备类型匹配确定，DT与所生成或接收的ID组合。组合的DT和ID作为传送到下一个设备的分组。在多个互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。参考提供给互连设备的设备类型，依次生成ID。将包含DT，ID和ID生成命令的SI以分组的形式发送到下一个设备。

85. 发明申请

US20080140899A1 ADDRESS ASSIGNMENT AND TYPE RECOGNITION OF SERIALLY INTERCONNECTED MEMORY DEVICES OF MIXED TYPE 失效
标题翻译：混合类型的串联互连存储器件的地址分配和类型识别
公开(公告)号：US20080140899A1
公开(公告)日：2008-06-12
申请号：US11771023
申请日：2007-06-29
申请人： HakJune OH , Hong Beom PYEON , Jin-Ki KIM
发明人： HakJune OH , Hong Beom PYEON , Jin-Ki KIM
IPC分类号： G06F13/00
CPC分类号： G11C7/20 , G06F12/0653 , G06F13/1694 , G11C7/10 , G11C8/12 , G11C8/18
摘要： A memory system architecture is provided in which a memory controller controls operations of memory devices in a serial interconnection configuration. The memory controller has an output serial interface for sending memory commands and an input serial interface for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, flash memory (e.g., NAND- and NOR-type flash memories). In an initialization phase, the memory devices are assigned with consecutive number addresses. The memory controller sends a target address and can recognize the type of the targeted memory device. A data path for the memory commands and the memory responses is provided by the interconnection.
摘要翻译：提供了存储器系统架构，其中存储器控制器控制串行互连配置中的存储器件的操作。存储器控制器具有用于发送存储器命令的输出串行接口和用于接收用于请求这样的响应的那些存储器命令的存储器响应的输入串行接口。每个存储器件包括存储器，例如闪速存储器（例如NAND和NOR型闪速存储器）。在初始化阶段，存储器设备被分配有连续的地址。存储器控制器发送目标地址并且可以识别目标存储器件的类型。存储器命令和存储器响应的数据路径由互连提供。

86. 发明申请

US20080080492A1 Packet based ID generation for serially interconnected devices 有权
标题翻译：用于串行互连设备的基于分组的ID生成
公开(公告)号：US20080080492A1
公开(公告)日：2008-04-03
申请号：US11529293
申请日：2006-09-29
申请人： Hong Beom Pyeon , HakJune Oh
发明人： Hong Beom Pyeon , HakJune Oh
IPC分类号： H04J1/16 , H04L12/56
CPC分类号： G06F1/12 , G06F1/04 , G11C5/00 , G11C5/066 , G11C7/20
摘要： Various memory devices (e.g., DRAMs, flash memories) are serially interconnected. The memory devices need their identifiers (IDs). Each of the memory devices generates IDs for neighboring memory devices. The IDs are generated synchronously with clock. Command data and previously generated ID data are synchronously registered. The registered data is synchronously output and provided as parallel data for calculation of a new ID for the neighboring device. The calculation is an addition or subtraction by one. The IDs are generated in a packet basis by interpreting serial packet-basis commands received at the serial input in response to clocks. A clock latency is controlled in response to the interpreted ID and the clock. In accordance with the controlled clock latency, a new ID is provided in a packet basis. In high frequency generation applications (e.g., 1 GHz), two adjacent devices connected in daisy chain fashion are guaranteed enough time margin to perform the interpretation of packet commands.
摘要翻译：各种存储器件（例如，DRAM，闪存）串联连接。存储器件需要其标识符（ID）。每个存储器件产生相邻存储器件的ID。 ID与时钟同步生成。命令数据和先前生成的ID数据被同步地注册。注册的数据被同步输出并作为用于计算相邻设备的新ID的并行数据提供。计算是一个加法或减法。通过解释响应于时钟在串行输入端接收的基于串行数据包的命令，以分组的形式生成ID。响应于解释的ID和时钟来控制时钟延迟。根据受控时钟延迟，以分组为基础提供新的ID。在高频产生应用（例如，1GHz）中，以菊链方式连接的两个相邻设备保证足够的时间余量来执行分组命令的解释。

87. 发明申请

US20080025457A1 Pulse counter with clock edge recovery 有权
标题翻译：脉冲计数器，带时钟沿恢复
公开(公告)号：US20080025457A1
公开(公告)日：2008-01-31
申请号：US11495609
申请日：2006-07-31
申请人： Hong Beom Pyeon
发明人： Hong Beom Pyeon
IPC分类号： H03K23/00
CPC分类号： H03K21/38
摘要： An apparatus and a method for counting input pulses during a specific time interval are provided. A clock edge recovery output signal is produced in response to an input gating signal and a clock signal containing the input pulses. The clock edge recovery output signal contains a respective full clock pulse for each of either the rising or falling edge of the input pulses of the clock signal that occurs while the input gating signal is in an enable state and when the input gating signal transitions from the enable state to the disable state. A counter circuit counts the pulses contained in the clock edge recovery output signal.
摘要翻译：提供了一种用于在特定时间间隔期间对输入脉冲进行计数的装置和方法。响应于输入门控信号和包含输入脉冲的时钟信号产生时钟沿恢复输出信号。时钟沿恢复输出信号包含相应的全时钟脉冲，用于在输入门控信号处于使能状态时发生的时钟信号的输入脉冲的上升沿或下降沿中的每一个，并且当输入选通信号从使能状态为禁用状态。计数器电路对包含在时钟沿恢复输出信号中的脉冲进行计数。

88. 发明申请

US20070286005A1 DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD FOR SELF-REFRESHING MEMORY CELLS WITH TEMPERATURE COMPENSATED SELF-REFRESH 有权
公开(公告)号：US20070286005A1
公开(公告)日：2007-12-13
申请号：US11835663
申请日：2007-08-08
申请人： Hong Beom PYEON
发明人： Hong Beom PYEON
IPC分类号： G11C11/34
CPC分类号： G11C11/406 , G11C7/04 , G11C11/40611 , G11C11/40615 , G11C11/40626 , G11C2211/4061
摘要： A dynamic random access memory (DRAM) device has an array of DRAM cells of rows by columns. Each DRAM cell of the array is coupled with a wordline of a corresponding row and a bitline of a corresponding column. An entry into and an exit from the self-refresh mode are detected by a mode detector and a self-refresh mode signal is provided. An oscillation circuit generates in response to the self-refresh mode signal generates a basic time period. A first frequency divider/time period multiplier changes the basic time period in accordance with a process variation factor relating to the DRAM device. A second frequency divider/time period multiplier further changes the changed time period in accordance with a temperature change factor relating to the DRAM device. In the self-refresh mode, data stored in the DRAM cells is refreshed. In accordance with the two factors, the DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time.

89. 发明授权

US07286377B1 Dynamic random access memory device and method for self-refreshing memory cells with temperature compensated self-refresh 有权
标题翻译：具有温度补偿自刷新功能的自动刷新存储单元的动态随机存取存储器件和方法
公开(公告)号：US07286377B1
公开(公告)日：2007-10-23
申请号：US11412960
申请日：2006-04-28
申请人： Hong Beom Pyeon
发明人： Hong Beom Pyeon
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/04 , G11C11/40611 , G11C11/40615 , G11C11/40626 , G11C2211/4061
摘要： A dynamic random access memory (DRAM) device has an array of DRAM cells of rows by columns. Each DRAM cell of the array is coupled with a wordline of a corresponding row and a bitline of a corresponding column. An entry into and an exit from the self-refresh mode are detected by a mode detector and a self-refresh mode signal is provided. An oscillation circuit generates in response to the self-refresh mode signal generates a basic time period. A first frequency divider/time period multiplier changes the basic time period in accordance with a process variation factor relating to the DRAM device. A second frequency divider/time period multiplier further changes the changed time period in accordance with a temperature change factor relating to the DRAM device. In the self-refresh mode, data stored in the DRAM cells is refreshed. In accordance with the two factors, the DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time.
摘要翻译：动态随机存取存储器（DRAM）器件具有逐列的DRAM单元阵列。阵列的每个DRAM单元与相应列的相应行和位线的字线相连。通过模式检测器检测进入和退出自刷新模式，并提供自刷新模式信号。响应于自刷新模式信号产生的振荡电路产生基本时间段。第一分频器/时间周期乘法器根据与DRAM器件有关的过程变化因素来改变基本时间周期。第二分频器/时间周期乘法器还根据与DRAM器件有关的温度变化因素来改变改变的时间周期。在自刷新模式下，存储在DRAM单元中的数据被刷新。根据这两个因素，DRAM器件执行并实现可变DRAM单元保留时间的可靠的自刷新。

90. 发明申请

US20070079147A1 Power up circuit with low power sleep mode operation 有权
标题翻译：通过低功耗睡眠模式操作启动电路
公开(公告)号：US20070079147A1
公开(公告)日：2007-04-05
申请号：US11238973
申请日：2005-09-30
申请人： Hong-Beom Pyeon , Peter Vlasenko
发明人： Hong-Beom Pyeon , Peter Vlasenko
IPC分类号： G06F1/00
CPC分类号： G06F1/24 , G06F1/3203 , H02J9/005
摘要： A power up circuit that having reduced power consumption during power saving modes, while maintaining an active flag signal indicating that the power supply voltage is satisfactory. This is achieved by turning off the power up circuit during the power saving mode, and using a status holding circuit to maintain the active flag signal in response to the power down signal. The status holding circuit is responsive to an internal node of the power up circuit for generating the active flag signal when the internal node has reached a predetermined level. The power down signal can be one or both a sleep mode signal and a deep power down signal. The status holding comprises an override circuit for maintaining the active flag signal in the power saving mode, and a restore circuit for rapidly resetting at least the internal node of the power up circuit upon exit of the power saving mode.
摘要翻译：一种在省电模式下降低功耗的上电电路，同时保持表示电源电压令人满意的有效标志信号。这是通过在省电模式期间关闭上电电路并且使用状态保持电路来响应于掉电信号来维持有效标志信号来实现的。状态保持电路响应于上电电路的内部节点，以在内部节点达到预定电平时产生有效标志信号。掉电信号可以是睡眠模式信号和深度掉电信号中的一个或两个。状态保持包括用于将有效标志信号保持在省电模式中的超控电路，以及用于在省电模式退出时至少快速复位上电电路的内部节点的恢复电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式