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1. 发明申请

US20180286472A1 Memory Module and Memory System 审中-公开
公开(公告)号：US20180286472A1
公开(公告)日：2018-10-04
申请号：US15996974
申请日：2018-06-04
申请人： Longitude Semiconductor S.a.r.l.
发明人： Yoshinori Matsui , Toshio Sugano , Hiroaki Ikeda
IPC分类号： G11C11/408 , G11C5/04 , H01L23/538 , G11C8/12 , G11C5/00 , H01L25/18 , H01L25/065 , G11C29/48 , G11C29/26 , G11C29/12 , G11C7/10 , G11C5/06
CPC分类号： G11C11/408 , G11C5/00 , G11C5/04 , G11C5/06 , G11C7/1051 , G11C7/1063 , G11C8/12 , G11C29/1201 , G11C29/26 , G11C29/48 , H01L23/5384 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2224/0401
摘要： In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

2. 发明授权

US09529713B2 Line termination methods and apparatus 有权
标题翻译：线路终端方法和设备
公开(公告)号：US09529713B2
公开(公告)日：2016-12-27
申请号：US14208965
申请日：2014-03-13
申请人： Micron Technology, Inc.
发明人： Terry Grunzke
IPC分类号： G06F12/10 , G06F12/06 , G11C16/06 , G11C5/00 , G11C7/10 , G11C7/20 , G11C7/22 , G06F13/18 , H04L25/02
CPC分类号： G06F12/0653 , G06F12/0661 , G06F13/16 , G06F13/18 , G11C5/00 , G11C7/10 , G11C7/20 , G11C7/22 , G11C16/06 , H04L25/0278 , H04L25/0298 , Y02D10/14
摘要： Methods and apparatus for termination of signal lines coupled to a number of memory devices are disclosed. One such method includes adjusting an input impedance of one or more terminals of an interface of a memory device in response to the memory device receiving a particular address. One such apparatus includes memory devices configured to selectively adjust an input impedance seen by one or more of the signal lines in response to receiving a particular address.
摘要翻译：公开了用于终止耦合到多个存储器件的信号线的方法和装置。一种这样的方法包括响应于存储器件接收特定地址来调整存储器件的接口的一个或多个端子的输入阻抗。一种这样的装置包括配置成响应于接收到特定地址而选择性地调整由一个或多个信号线看到的输入阻抗的存储器件。

3. 发明授权

US09275689B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09275689B2
公开(公告)日：2016-03-01
申请号：US14598836
申请日：2015-01-16
申请人： Renesas Electronics Corporation
发明人： Masahiro Ito
IPC分类号： G11C5/10 , G11C11/408 , H01L23/498 , G11C5/00 , H01L25/065 , H01L25/18 , G11C5/02 , G11C5/06 , H01L23/12 , H05K1/02 , H05K1/00
CPC分类号： G11C5/10 , G11C5/00 , G11C5/025 , G11C5/063 , G11C11/408 , H01L23/12 , H01L23/49816 , H01L23/49838 , H01L25/0655 , H01L25/18 , H01L2224/16225 , H05K1/00 , H05K1/02 , H05K1/0213
摘要： Provided is a semiconductor device capable of increasing the number of signals. A semiconductor device according to an embodiment of the invention includes memories; a controller that designates addresses of the memories; amounting board having lines formed thereon, the lines connecting the controller with the memories; and a first ball group that connects the controller with the lines of the mounting board. A plurality of address lines formed on the mounting board includes an address line formed of a front surface wiring layer, and an address line formed of a back surface wiring layer. In each of the front surface wiring layer and the back surface wiring layer, each of the address lines from first balls of the first ball group is routed in order from a first memory to a fourth memory.
摘要翻译：提供能够增加信号数量的半导体器件。根据本发明实施例的半导体器件包括存储器; 指定存储器的地址的控制器; 其上形成线，其中控制器与存储器连接的线; 以及将控制器与安装板的线路连接的第一球组。形成在安装基板上的多个地址线包括由正面布线层形成的地址线和由背面布线层形成的地址线。在前表面布线层和背面布线层的每个中，从第一存储器到第四存储器的顺序路由从第一球组的第一球的每个地址线。

4. 发明申请

US20150316607A1 SYSTEM AND METHOD FOR CONVERGING CURRENT WITH TARGET CURRENT IN DEVICE UNDER TEST 有权
标题翻译：用于在测试装置中用目标电流进行电流的电流的系统和方法
公开(公告)号：US20150316607A1
公开(公告)日：2015-11-05
申请号：US14265772
申请日：2014-04-30
申请人： Keysight Technologies, Inc.
发明人： Katsuhito Iwasaki , Masaharu Goto , Tomonori Ura
IPC分类号： G01R31/28
CPC分类号： G01R31/2621 , G01R1/00 , G01R31/2633 , G01R31/2832 , G01R31/2851 , G11C5/00 , H03F2200/00 , H03K2217/00
摘要： A test system measures parameters of a device under test (DUT), including a transistor. The test system includes a first voltage source unit for supplying a gate voltage; a second voltage source unit for supplying one of a drain voltage or a source voltage, the second voltage source having a current measurement device for detecting one of a drain current or a source current flowing through the transistor, respectively; a feedback unit for outputting a feedback current, based on the one of the drain or source currents; and an error amplifier for outputting a feedback control signal, based on comparison of the feedback current and a target current value. The first voltage source unit adjusts the gate voltage based on the feedback control signal so that the one of the drain or source currents converges to match the target current value.
摘要翻译：测试系统测量被测器件（DUT）的参数，包括晶体管。测试系统包括用于提供栅极电压的第一电压源单元; 用于提供漏极电压或源极电压之一的第二电压源单元，所述第二电压源具有用于分别检测流过所述晶体管的漏极电流或源极电流之一的电流测量装置; 反馈单元，用于基于所述漏极或源极电流之一输出反馈电流; 以及误差放大器，用于基于反馈电流和目标电流值的比较来输出反馈控制信号。第一电压源单元基于反馈控制信号来调节栅极电压，使得漏极或源电流之一收敛以匹配目标电流值。

5. 发明申请

US20150178197A1 Addressing Auto address Assignment and Auto-Routing in NAND Memory Network 有权
标题翻译：在NAND存储器网络中寻址自动地址分配和自动路由
公开(公告)号：US20150178197A1
公开(公告)日：2015-06-25
申请号：US14139164
申请日：2013-12-23
申请人： SanDisk Technologies Inc.
发明人： Eugene Jinglun Tam
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F2212/1016 , G06F2212/2022 , G11C5/00 , G11C8/12 , G11C29/83 , G11C29/88
摘要： A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes, including pass-through and active modes. Techniques are presented for the addressing of memory chips within such a topology, including an address assignment scheme.
摘要翻译：用于非易失性存储器系统的存储器电路的拓扑降低了电容负载。对于给定的通道，单个存储器芯片可以连接到控制器，但是又连接到以树状结构扇出的多个其他存储器件，其也可以回到单个存储器件。除了诸如存储器阵列和相关联的外围电路的通常的电路之外，存储器芯片还包括触发器电路，并且可以在多种模式中起作用，包括直通和活动模式。介绍了在这样的拓扑中寻址存储器芯片的技术，包括地址分配方案。

6. 发明授权

US09037783B2 Non-volatile memory device having parallel queues with respect to concurrently addressable units, system including the same, and method of operating the same 有权
标题翻译：具有相对于可寻址单元的并行队列的非易失性存储器件，包括其的系统及其操作方法
公开(公告)号：US09037783B2
公开(公告)日：2015-05-19
申请号：US13713377
申请日：2012-12-13
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Seung-Wan Koh , Tae-Kyeong Ko
IPC分类号： G06F12/02 , G11C5/00
CPC分类号： G06F12/0246 , G06F2212/7208 , G11C5/00
摘要： A non-volatile memory device having respective parallel queues is disclosed. The non-volatile memory device includes a plurality of concurrently addressable units. The non-volatile memory device has respective queues for the concurrently addressable units, and transfers a second command to respective queues for the remaining concurrently addressable units while a first command is executed in a part of the concurrently addressable units, and executes a second command in the remaining concurrently addressable units. Accordingly, non-volatile memory device may concurrently access the concurrently addressable units in parallel, and may have high speed.
摘要翻译：公开了具有各自的并行队列的非易失性存储器件。非易失性存储器件包括多个可同时寻址的单元。非易失性存储器件具有用于同时可寻址单元的各自的队列，并且在同时可寻址单元的一部分中执行第一命令时，将第二命令传送到剩余的可寻址单元的各个队列，并且执行第二命令剩余的可寻址单元。因此，非易失性存储装置可以并行地同时访问同时可寻址单元，并且可以具有高速度。

7. 发明申请

US20140152382A1 RECONFIGURABLE SWITCHED-CAPACITOR VOLTAGE CONVERTER CIRCUIT, INTEGRATED CIRCUIT (IC) CHIP INCLUDING THE CIRCUIT AND METHOD OF SWITCHING VOLTAGE ON CHIP 有权
公开(公告)号：US20140152382A1
公开(公告)日：2014-06-05
申请号：US13727580
申请日：2012-12-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Leland Chang , Robert Montoye , Jae-sun Seo
IPC分类号： G05F3/02
CPC分类号： G11C5/00 , G11C5/147 , G11C5/148 , H02M3/07 , H02M2003/072
摘要： A configurable-voltage converter circuit that may be CMOS and an integrated circuit chip including the converter circuit and method of operating the IC chip and circuit. A transistor totem, e.g., of 6 or more field effect transistors, PFETs and NFETs, connected (PNPNPN) between a first supply (Vin) line and a supply return line. A first switching capacitor is connected between first and second pairs of totem PN FETs pair of transistors. A second switching capacitor is connected between the second and a third pair of totem FETs. A configuration control selectively switches both third FETs off to float the connected end of the second capacitor, thereby switching voltage converter modes.

8. 发明申请

US20140146461A1 Secondary Memory Device 有权
标题翻译：辅助存储设备
公开(公告)号：US20140146461A1
公开(公告)日：2014-05-29
申请号：US14087095
申请日：2013-11-22
申请人： Samsung Electronics Co., Ltd.
发明人： Jin-young Choi , Joon-young Oh , Hee-youb Kang , Jung-hoon Kim , Won-hwa Lee , Jae-beom Byun , Jong-yun Yun
IPC分类号： H05K7/20
CPC分类号： G06F1/187 , G06F1/203 , G11B2220/60 , G11C5/00 , G11C5/02 , G11C5/025 , H05K7/20445
摘要： A secondary memory device includes: a substrate and a housing configured to accommodate at least a part of the substrate. The substrate has upper and lower opposed surfaces and includes a first region in which a first semiconductor device is mounted on the upper surface and a second region in which a second semiconductor device is mounted on the upper surface. The housing includes a first sub-housing covering the upper surface of the substrate at the first region and the first semiconductor device. The first sub-housing does not extend to cover the upper surface of the substrate at the second region.
摘要翻译：辅助存储器件包括：衬底和被配置为容纳衬底的至少一部分的壳体。基板具有上下相对的表面，并且包括其第一半导体器件安装在上表面上的第一区域和第二半导体器件安装在上表面上的第二区域。壳体包括覆盖第一区域的基板的上表面的第一子壳体和第一半导体器件。第一子壳体不延伸以在第二区域覆盖基板的上表面。

9. 发明申请

US20140077891A1 CRYSTAL OSCILLATOR EMULATOR WITH EXTERNALLY SELECTABLE OPERATING CONFIGURATIONS 审中-公开
标题翻译：具有外部选择性操作配置的水晶振荡器仿真器
公开(公告)号：US20140077891A1
公开(公告)日：2014-03-20
申请号：US14089261
申请日：2013-11-25
申请人： Marvell World Trade Ltd.
发明人： Sehat Sutardja
IPC分类号： H03B5/04
CPC分类号： H03L1/026 , G11C5/00 , G11C5/143 , H01L23/10 , H01L23/315 , H01L23/345 , H01L23/5227 , H01L2224/05553 , H01L2224/48247 , H01L2224/49175 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H03B5/04 , H03B5/36 , H03L1/027 , H03L1/04 , H03L7/07 , H03L7/0891 , H03L7/099 , H03L7/1976 , H01L2924/00
摘要： A crystal oscillator emulator having a plurality of predetermined operating configurations. The crystal oscillator emulator includes a measurement circuit configured to measure a value of an impedance connected to a select pin of the crystal oscillator emulator, wherein the impedance is external to the crystal oscillator emulator, and generate an output having a value corresponding to the value of the impedance. The storage circuit is configured to store a plurality of values corresponding to the plurality of predetermined operating configurations and select one of the plurality of values based on the output of the measurement circuit. A controller is configured to set an output frequency of the crystal oscillator emulator based on the selected one of the plurality of values.
摘要翻译：一种具有多个预定操作配置的晶体振荡器模拟器。晶体振荡器模拟器包括测量电路，其被配置为测量连接到晶体振荡器仿真器的选择引脚的阻抗的值，其中阻抗在晶体振荡器模拟器外部，并且产生具有对应于阻抗。存储电路被配置为存储对应于多个预定操作配置的多个值，并且基于测量电路的输出来选择多个值中的一个。控制器被配置为基于所选择的多个值中的一个来设置晶体振荡器仿真器的输出频率。

10. 发明申请

US20130268721A1 NON-VOLATILE MEMORY DEVICE HAVING PARALLEL QUEUES WITH RESPECT TO CONCURRENTLY ADDRESSABLE UNITS, SYSTEM INCLUDING THE SAME, AND METHOD OF OPERATING THE SAME 有权
标题翻译：具有相同可寻址单元的并行串联的非易失性存储器件，包括其的系统及其操作方法
公开(公告)号：US20130268721A1
公开(公告)日：2013-10-10
申请号：US13713377
申请日：2012-12-13
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Seung-Wan KOH , Tae-Kyeong KO
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7208 , G11C5/00
摘要： A non-volatile memory device having respective parallel queues is disclosed. The non-volatile memory device includes a plurality of concurrently addressable units. The non-volatile memory device has respective queues for the concurrently addressable units, and transfers a second command to respective queues for the remaining concurrently addressable units while a first command is executed in a part of the concurrently addressable units, and executes a second command in the remaining concurrently addressable units. Accordingly, non-volatile memory device may concurrently access the concurrently addressable units in parallel, and may have high speed.
摘要翻译：公开了具有各自的并行队列的非易失性存储器件。非易失性存储器件包括多个可同时寻址的单元。非易失性存储器件具有用于同时可寻址单元的各自的队列，并且在同时可寻址单元的一部分中执行第一命令时，将第二命令传送到剩余的可寻址单元的各个队列，并且执行第二命令剩余的可寻址单元。因此，非易失性存储装置可以并行地同时访问同时可寻址单元，并且可以具有高速度。

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