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81. 发明授权

US07385843B2 Multi-state memory 有权
公开(公告)号：US07385843B2
公开(公告)日：2008-06-10
申请号：US11243344
申请日：2005-10-03
申请人： Daniel C. Guterman , Yupin Kawing Fong
发明人： Daniel C. Guterman , Yupin Kawing Fong
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0425 , G11C16/0441 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/349 , G11C16/3495 , G11C27/005 , G11C29/00 , G11C29/76 , G11C2211/5634 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.

82. 发明授权

US07317638B2 Efficient verification for coarse/fine programming of non-volatile memory 有权
标题翻译：对非易失性存储器进行粗/精编程的高效验证
公开(公告)号：US07317638B2
公开(公告)日：2008-01-08
申请号：US11550502
申请日：2006-10-18
申请人： Daniel C. Guterman , Nima Mokhlesi , Yupin Fong
发明人： Daniel C. Guterman , Nima Mokhlesi , Yupin Fong
IPC分类号： G11C16/12 , G11C16/10 , G11C16/28 , G11C16/26
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/3454 , G11C16/3481 , G11C2211/5621 , G11C2211/5624
摘要： A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.
摘要翻译：通过首先执行粗略编程处理并随后执行精细编程处理来编程非易失性存储器件。通过使用有效的验证方案来增强粗/精编程方法，该验证方案允许对粗略编程过程验证一些非易失性存储器单元，同时验证其它非易失性存储器单元用于精细编程过程。精细的编程过程可以使用电流吸收，电荷分组测量或其他合适的方法来完成。

83. 发明授权

US07243275B2 Smart verify for multi-state memories 有权
标题翻译：智能验证多状态存储器
公开(公告)号：US07243275B2
公开(公告)日：2007-07-10
申请号：US11304961
申请日：2005-12-14
申请人： Geoffrey S. Gongwer , Daniel C. Guterman , Yupin Kawing Fong
发明人： Geoffrey S. Gongwer , Daniel C. Guterman , Yupin Kawing Fong
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C11/5635 , G11C11/5628 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： A “smart verify” technique, whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations, is presented. This technique can increase multi-state write speed while maintaining reliable operation within sequentially verified, multi-state memory implementations by providing “intelligent” element to minimize the number of sequential verify operations for each program/verify/lockout step of the write sequence. At the beginning of a program/verify cycle sequence only the lowest state or states are checked during the verify phase. As lower states are reached, additional higher states are added to the verify sequence and lower states can be removed.
摘要翻译：提出了一种“智能验证”技术，其中使用基于验证结果的动态调整多状态验证范围对基于顺序状态的验证实现来编程多状态存储器。该技术可以通过提供“智能”元件来最小化写入序列的每个程序/验证/锁定步骤的顺序验证操作的数量，从而提高多状态写入速度，同时在顺序验证的多状态存储器实现中保持可靠的操作。在程序/验证周期序列的开始，在验证阶段只检查最低的状态或状态。当达到较低的状态时，额外的更高的状态被添加到验证序列中，并且可以去除较低的状态。

84. 发明授权

US07230851B2 Reducing floating gate to floating gate coupling effect 有权
标题翻译：降低浮栅耦合效应
公开(公告)号：US07230851B2
公开(公告)日：2007-06-12
申请号：US11021872
申请日：2004-12-23
申请人： Yupin Fong , Daniel C. Guterman
发明人： Yupin Fong , Daniel C. Guterman
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/16
摘要： For a non-volatile memory system, compressing the erase threshold voltage distribution into the lowest threshold voltage state will decrease the valid data threshold voltage window. Decreasing the valid data threshold voltage window reduces the floating gate to floating gate coupling effect. The compression can be performed as part of the erase process or part of the programming operation.
摘要翻译：对于非易失性存储器系统，将擦除阈值电压分布压缩到最低阈值电压状态将降低有效的数据阈值电压窗口。降低有效的数据阈值电压窗口可以将浮栅减少到浮栅耦合效应。压缩可以作为擦除过程的一部分或编程操作的一部分来执行。

85. 发明授权

US07139198B2 Efficient verification for coarse/fine programming of non-volatile memory 有权
标题翻译：对非易失性存储器进行粗/精编程的高效验证
公开(公告)号：US07139198B2
公开(公告)日：2006-11-21
申请号：US10766217
申请日：2004-01-27
申请人： Daniel C. Guterman , Nima Mokhlesi , Yupin Fong
发明人： Daniel C. Guterman , Nima Mokhlesi , Yupin Fong
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/3454 , G11C16/3481 , G11C2211/5621 , G11C2211/5624
摘要： A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.
摘要翻译：通过首先执行粗略编程处理并随后执行精细编程处理来编程非易失性存储器件。通过使用有效的验证方案来增强粗/精编程方法，该验证方案允许对粗略编程过程验证一些非易失性存储器单元，同时验证其它非易失性存储器单元用于精细编程过程。精细的编程过程可以使用电流吸收，电荷分组测量或其他合适的方法来完成。

86. 发明授权

US07092292B2 Noise reduction technique for transistors and small devices utilizing an episodic agitation 有权
公开(公告)号：US07092292B2
公开(公告)日：2006-08-15
申请号：US10976692
申请日：2004-10-28
申请人： Nima Mokhlesi , Daniel C. Guterman , Geoffrey S. Gongwer
发明人： Nima Mokhlesi , Daniel C. Guterman , Geoffrey S. Gongwer
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C16/0458 , G11C16/26
摘要： The present invention presents methods for reducing the amount of noise inherent in the reading of a non-volatile storage device by applying an episodic agitation (e.g. a time varying voltage) to some terminal(s) of the cell as part of the reading process. Various aspects of the present invention also extend to devices beyond non-volatile memories. According to one aspect of the present invention, in addition to the normal voltage levels applied to the cell as part of the reading process, a time varying voltage is applied to the cell. A set of exemplary embodiments apply a single or multiple set of alternating voltages to one or more terminals of a floating gate memory cell just prior to or during the signal integration time of a read process. In other embodiments, other reproducible external or internal agitations which are repeatable, and whose average effect (from one integration time to the next integration time) remains sufficiently constant so as to have a net noise reduction effect is applicable.

87. 发明授权

US07023733B2 Boosting to control programming of non-volatile memory 有权
标题翻译：促进控制非易失性存储器的编程
公开(公告)号：US07023733B2
公开(公告)日：2006-04-04
申请号：US10839764
申请日：2004-05-05
申请人： Daniel C. Guterman , Nima Mokhlesi , Yupin Fong
发明人： Daniel C. Guterman , Nima Mokhlesi , Yupin Fong
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/12 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3454 , G11C16/3459
摘要： A system is disclosed for programming non-volatile memory with greater precision. In one embodiment, the system includes applying a first phase of a boosting signal to one or more unselected word lines for a set of NAND strings, applying a programming level to selected bit lines of the NAND strings while applying the first phase of the boosting signal, and applying an inhibit level to unselected bit lines of the NAND strings while applying the first phase of the boosting signal. Subsequently, a second phase of the boosting signal is applied to the one or more unselected word lines and the signal(s) on the selected bit lines are changed by applying the inhibit level to the selected bit lines so that NAND strings associated with the selected bit lines will be boosted by the second phase of the boosting signal. A program voltage signal is applied to a selected word line in order to program storage elements connected to the selected word line.
摘要翻译：公开了一种更精确地编程非易失性存储器的系统。在一个实施例中，该系统包括将一个升压信号的第一相位应用于一组NAND串的一个或多个未选字线，将编程电平施加到NAND串的选定位线，同时施加升压信号的第一相位并且在施加升压信号的第一相位时将禁止电平施加到NAND串的未选位线。随后，将升压信号的第二相位施加到一个或多个未选字线，并且通过将所述禁止电平施加到所选择的位线来改变所选位线上的信号，使得与所选择的位线相关联的NAND串位线将由升压信号的第二阶段提升。将程序电压信号施加到所选择的字线，以便编程连接到所选字线的存储元件。

88. 发明授权

US07020026B2 Bitline governed approach for program control of non-volatile memory 有权
标题翻译：用于非易失性存储器程序控制的位线控制方法
公开(公告)号：US07020026B2
公开(公告)日：2006-03-28
申请号：US10839806
申请日：2004-05-05
申请人： Daniel C. Guterman , Nima Mokhlesi , Yupin Fong
发明人： Daniel C. Guterman , Nima Mokhlesi , Yupin Fong
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/12 , G11C16/30 , G11C16/3454 , G11C16/3459
摘要： In a system for programming non-volatile storage, technology is disclosed for programming with greater precision and reasonable program times. In one embodiment, a first voltage is applied to a bit line for a first non-volatile storage element in order to inhibit that first non-volatile storage element. A first program voltage is applied to the first non-volatile storage element. For example, a program pulse is applied to a control gate for the first non-volatile storage element. During the program pulse, the bit line is changed from said first voltage to a second voltage, where the second voltage allows the first non-volatile storage element to be programmed.
摘要翻译：在用于编程非易失性存储器的系统中，公开了用于以更高的精度和合理的程序时间进行编程的技术。在一个实施例中，第一电压被施加到用于第一非易失性存储元件的位线，以便禁止第一非易失性存储元件。第一编程电压被施加到第一非易失性存储元件。例如，将编程脉冲施加到第一非易失性存储元件的控制栅极。在编程脉冲期间，位线从所述第一电压改变到第二电压，其中第二电压允许第一非易失性存储元件被编程。

89. 发明授权

US07002843B2 Variable current sinking for coarse/fine programming of non-volatile memory 失效
公开(公告)号：US07002843B2
公开(公告)日：2006-02-21
申请号：US10766786
申请日：2004-01-27
申请人： Daniel C. Guterman , Nima Mokhlesi , Yupin Fong
发明人： Daniel C. Guterman , Nima Mokhlesi , Yupin Fong
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3454 , G11C16/3481 , G11C27/005
摘要： A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.

90. 发明授权

US06977844B2 Method of reducing disturbs in non-volatile memory 失效
标题翻译：减少非易失性存储器中的干扰的方法
公开(公告)号：US06977844B2
公开(公告)日：2005-12-20
申请号：US11054084
申请日：2005-02-08
申请人： Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
发明人： Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
IPC分类号： G11C16/02 , G11C16/12 , G11C16/04
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.
摘要翻译：在非易失性存储器中，在阵列位线上的电压电平改变时产生的未选择字线中产生的位移电流可能导致干扰。提出了减少这些电流的技术。在第一方面，减少了在字线上同时编程的单元的数量。在非易失性存储器中，存储器单元阵列由多个单元组成，并且单元被组合成共享公共字线的平面，避免同一平面内的单元的同时编程。多个单元可以并行编程，但是它们被布置成处于分开的平面中。这是通过选择并行编程的单元数量及其顺序，使得所有编程在一起的单元都来自不同的平面，通过比较要编程的单元以查看是否来自同一平面，或者组合这些。在第二个互补方面，位线上的电压电平改变的速率是可调节的。通过监视干扰的频率，或者基于设备的应用，可以调整位线驱动器改变位线电压的速率。这可以通过外部设置速率或由控制器基于设备性能和产生的数据错误量来实现。

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