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1. 发明授权

US11783907B2 Iterative programming of analog content addressable memory 有权
公开(公告)号：US11783907B2
公开(公告)日：2023-10-10
申请号：US17514847
申请日：2021-10-29
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： Giacomo Pedretti , John Paul Strachan , Catherine Graves
IPC分类号： G11C27/00 , G11C15/04
CPC分类号： G11C27/005 , G11C15/046
摘要： Embodiments of the disclosure provide a system, method, or computer readable medium for programming a target analog voltage range of an analog content addressable memory (aCAM) row. The method may comprise calculating a threshold current sufficient to switch a sense amplifier (SA) on and discharge a match line (ML) connected to a cell of the aCAM; and based on calculating the threshold current, programming a match threshold value by setting a memristor conductance in association with the target analog voltage range applied to a data line (DL) input. The target analog voltage range may comprise a target analog voltage range vector.

2. 发明授权

US11735281B2 Analog content addressable memory with analog input and analog output 有权
公开(公告)号：US11735281B2
公开(公告)日：2023-08-22
申请号：US17245540
申请日：2021-04-30
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： Catherine Graves , Can Li , John Paul Strachan
IPC分类号： G11C27/00 , G11C15/04
CPC分类号： G11C27/005 , G11C15/046
摘要： An analog content addressable memory (aCAM) that enables parallel searching of analog ranges of values and generates analog outputs that quantify matches between input data and stored data is disclosed. The input data can be compared with the stored data, and the input data can be determined to match the stored data based on a value associated with the input data being within a range associated with the stored data. The aCAM can generate an analog output that represents a number of matches and a number of mismatches between the input data and the stored data. Based on the analog output, whether the input data matches the stored data and a degree to which the input data matches the stored data can be determined.

3. 发明授权

US10847238B2 Analog, non-volatile, content addressable memory 有权
公开(公告)号：US10847238B2
公开(公告)日：2020-11-24
申请号：US16274379
申请日：2019-02-13
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： Can Li , Catherine Graves , John Paul Strachan
IPC分类号： G11C27/00 , G11C15/04 , G11C11/16 , G11C13/00
CPC分类号： G11C27/005 , G11C11/16 , G11C13/0004 , G11C13/0007 , G11C15/046
摘要： An analog content addressable memory cell includes a high side and a low side. The high side encodes a high bound on a range of values and includes a first voltage divider formed of a first programmable resistor and a first electronically controlled variable resistor. The low side encodes a low bound on the range of values and includes a second voltage divider formed of a second programmable resistor and a second electronically controlled variable resistor.

4. 发明授权

US09874856B2 EEPROM cell with charge loss 有权
公开(公告)号：US09874856B2
公开(公告)日：2018-01-23
申请号：US14883364
申请日：2015-10-14
申请人： STMicroelectronics (Rousset) SAS
发明人： Pascal Fornara
IPC分类号： G11C16/04 , H01L27/115 , G04F10/10 , G11C16/28 , G11C16/34 , G11C27/00 , H01L21/28 , H01L27/11521 , H01L27/11524 , H01L29/66 , H01L29/788 , H01L29/51
CPC分类号： G04F10/10 , G11C16/0433 , G11C16/0441 , G11C16/28 , G11C16/349 , G11C27/005 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/511 , H01L29/518 , H01L29/66825 , H01L29/788
摘要： An EEPROM memory cell includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer. The insulation layer includes a first portion and a second portion having lower insulation properties than the first one. The second portion is located at least partially above a channel region of the transistor.

5. 发明授权

US09696918B2 Protection and recovery from sudden power failure in non-volatile memory devices 有权
公开(公告)号：US09696918B2
公开(公告)日：2017-07-04
申请号：US14523979
申请日：2014-10-27
申请人： APPLE INC.
发明人： Etai Zaltsman , Avraham Poza Meir
IPC分类号： G06F12/02 , G06F3/06 , G11C11/56 , G06F11/14 , G11C16/22 , G11C27/00
CPC分类号： G06F3/0619 , G06F3/0625 , G06F3/0634 , G06F3/0659 , G06F3/0688 , G06F11/1441 , G11C11/5628 , G11C16/22 , G11C16/225 , G11C27/005 , G11C2211/5641
摘要： A method for data storage includes, for a memory including groups of memory cells, defining a normal mode and a protected mode, wherein in the protected mode a respective analog value of each memory cell remains at all times unambiguously indicative of a respective data value stored in that memory cell. Data is initially stored in the memory using the normal mode. In response to an event, the protected mode is reverted to for at least one of the groups of the memory cells.

6. 发明授权

US09640263B2 Non-volatile memory systems and methods 有权
公开(公告)号：US09640263B2
公开(公告)日：2017-05-02
申请号：US14140452
申请日：2013-12-24
申请人： Silicon Storage Technology, Inc.
发明人： Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G11C11/34 , G11C16/10 , G11C11/56 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/00 , G11C13/00
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

7. 发明申请

US20170004865A1 SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE 有权
标题翻译：半导体器件，电子元件和电子器件
公开(公告)号：US20170004865A1
公开(公告)日：2017-01-05
申请号：US15125658
申请日：2015-03-05
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Shuhei Nagatsuka , Tomoaki Atsumi , Shunpei Yamazaki
IPC分类号： G11C7/22 , G11C5/14
CPC分类号： G11C7/22 , G11C5/14 , G11C11/405 , G11C11/565 , G11C27/005 , H01L27/0688 , H01L27/088 , H01L27/108 , H01L27/1156 , H01L27/1225 , H01L29/786
摘要： A semiconductor device which can write and read multilevel data is provided. Anode connecting a source or a drain of an OS transistor and a gate of an OS transistor can hold the distribution of a plurality of potentials. A circuit configuration is employed in which the potential of the node is changed by capacitive coupling to control a conduction state of the OS transistor whose gate is connected thereto so that the potential of a gate of a Si transistor is changed. The potential of the gate of the Si transistor is changed positively in accordance with the potential change by capacitive coupling and is changed negatively in accordance with another transistor. In accordance with a change in value of current flowing through the Si transistor is detected, written data is read.
摘要翻译：提供了可以写入和读取多级数据的半导体器件。连接OS晶体管的源极或漏极和OS晶体管的栅极的阳极可以保持多个电位的分布。采用电路结构，其中通过电容耦合来改变节点的电位，以控制其栅极连接到其上的OS晶体管的导通状态，使得Si晶体管的栅极的电位改变。 Si晶体管的栅极的电位根据电容耦合的电位变化而正向变化，并根据另一个晶体管呈负变化。根据检测到流过Si晶体管的电流值的变化，读取写入的数据。

8. 发明授权

US09502120B2 Programming memory cells dependent upon distortion estimation 有权
标题翻译：根据失真估计编程存储单元
公开(公告)号：US09502120B2
公开(公告)日：2016-11-22
申请号：US14318876
申请日：2014-06-30
申请人： Apple Inc.
发明人： Yoav Kasorla , Naftali Sommer , Eyal Gurgi , Micha Anholt
IPC分类号： G11C16/10 , G11C27/00 , G06F11/10 , G11C11/56 , G11C16/04 , G11C16/12
CPC分类号： G11C27/005 , G06F11/1048 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C2211/5647 , G11C2211/5648
摘要： A method for data storage includes accepting data for storage in an array of memory cells, which are arranged in rows associated with respective word lines. Data is stored in one or more memory cells of the array using one or more programming levels. In response to a determination that a first memory cell of the one or more memory cells is subject to distortion, a second memory cell may be programmed to a predetermined programming level.
摘要翻译：一种用于数据存储的方法包括接收用于存储在与各个字线相关联的行中的存储器单元阵列中的数据。使用一个或多个编程级别将数据存储在阵列的一个或多个存储单元中。响应于确定一个或多个存储器单元的第一存储器单元经历失真，第二存储器单元可被编程为预定的编程级别。

9. 发明申请

US20160099073A1 HIGHLY LINEAR ANALOG-TO-DIGITAL CONVERTER AND METHOD FOR NONVOLATILE MEMORY 有权
标题翻译：非线性模拟数字转换器和非易失性存储器的方法
公开(公告)号：US20160099073A1
公开(公告)日：2016-04-07
申请号：US14508274
申请日：2014-10-07
申请人： SANDISK TECHNOLOGIES, INC.
发明人： RAUL ADRIAN CERNEA
IPC分类号： G11C16/32
CPC分类号： G11C16/32 , G11C7/16 , G11C7/18 , G11C11/5628 , G11C16/10 , G11C16/28 , G11C16/3454 , G11C27/005 , G11C2211/5621 , H03M1/56
摘要： A non-volatile memory has an ADC that digitizes an analog voltage in a range delimited by V1 and V2 into N intervals, resulting in a digital Vx with x between 1 to N. A ramp voltage Vramp(x) calibrated to rise linearly from V1 to V2 in x=1 to N clock cycles is used to scan the analog voltage. Vx is then given by Vx=Vramp(x). The ramp voltage is provided by a constant current charging a capacitor and has a slope proportional to a DAC resistor, R(x) that is programmable from 1 to N. In a calibration mode, the R(x) is set to N, which results in K clock cycles spanning V1 to V2. In a subsequent normal mode, the DAC resistor is reset to R(K) to result in a calibrated ramp voltage that would rise from V1 to V2 in N clock cycles.
摘要翻译：非易失性存储器具有将由V1和V2限定的范围内的模拟电压数字化为N个间隔的ADC，导致x在1至N之间的数字Vx。斜坡电压Vramp（x）被校准为从V1线性上升到x = 1到N个时钟周期的V2用于扫描模拟电压。 Vx由Vx = Vramp（x）给出。斜坡电压由对电容充电的恒定电流提供，并且具有与DAC电阻成比例的斜率，R（x）可编程为1至N.在校准模式中，R（x）设置为N，其中导致跨越V1到V2的K个时钟周期。在随后的正常模式下，DAC电阻复位为R（K），导致在N个时钟周期内从V1升高到V2的校准斜坡电压。

10. 发明授权

US09269427B2 Memory devices and related methods 有权
标题翻译：内存设备及相关方法
公开(公告)号：US09269427B2
公开(公告)日：2016-02-23
申请号：US14325675
申请日：2014-07-08
申请人： Peter K. Nagey
发明人： Peter K. Nagey
IPC分类号： G11C11/16 , G11C13/00 , G11C11/56 , G11C27/00
CPC分类号： G11C13/0021 , G11C11/165 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C11/5642 , G11C13/0002 , G11C13/004 , G11C27/005
摘要： A resistive memory device. Implementations may include an array of memory cells including resistive memory elements which are coupled to isolation transistors and which may include a magnetic tunnel junction. A decoder decodes input address information to select a row of the array. A binarizer coupled to the memory array assigns binary weights to outputs of the memory array output through bit lines coupled to the memory cells. A summer sums the binary weighted outputs, and a quantizer generates an output digital code corresponding to data stored in a plurality of memory cells during a prior program cycle. The outputs of the memory array may be currents or voltages. In implementations multiple arrays of memory cells may be utilized and their respective outputs combined to form higher bit outputs, such as eight bit, twelve bit, sixteen bit, and so forth.
摘要翻译：电阻式存储器件。实施方案可以包括存储单元的阵列，包括耦合到隔离晶体管并且可以包括磁性隧道结的电阻性存储器元件。解码器解码输入地址信息以选择阵列的一行。耦合到存储器阵列的二进制化器通过耦合到存储器单元的位线将二进制权重分配给存储器阵列输出的输出。夏季对二进制加权输出求和，并且量化器在先前的程序周期期间生成对应于存储在多个存储单元中的数据的输出数字代码。存储器阵列的输出可以是电流或电压。在实现中，可以使用多个存储器单元阵列，并且它们各自的输出组合以形成较高位输出，例如8位，12位，16位等等。

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