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81. 发明申请

US20150340483A1 Group III-V Device Including a Shield Plate 审中-公开
标题翻译：包含屏蔽板的III-V组装置
公开(公告)号：US20150340483A1
公开(公告)日：2015-11-26
申请号：US14707966
申请日：2015-05-08
申请人： International Rectifier Corporation
发明人： Michael A. Briere
IPC分类号： H01L29/778 , H01L29/10 , H01L29/40 , H01L29/20 , H01L29/205
CPC分类号： H01L29/205 , H01L29/1075 , H01L29/2003 , H01L29/402 , H01L29/404 , H01L29/41758 , H01L29/7783
摘要： There are disclosed herein various implementations of a group III-V device including a shield plate. Such a group III-V device includes a substrate, a transition body situated over the substrate, a device channel layer situated over the transition body, and a device barrier layer situated over the device channel layer and producing a device two-dimensional electron gas (2-DEG). The group III-V device also includes a drain electrode coupled to the device barrier layer, and a shield plate, which may be coupled to the drain electrode or may be a floating shield plate. The shield plate is configured to substantially shield the device 2-DEG from charge centers situated over the device barrier layer.
摘要翻译：这里公开了包括屏蔽板的III-V族装置的各种实施方式。这种组III-V器件包括衬底，位于衬底上方的过渡体，位于过渡体上方的器件沟道层，以及位于器件沟道层上方并产生器件二维电子气的器件阻挡层 2-DEG）。 III-V族器件还包括耦合到器件阻挡层的漏电极和可以连接到漏电极的屏蔽板，或者可以是浮动屏蔽板。屏蔽板被配置为基本上屏蔽设备2°与装置阻挡层上方的电荷中心。

82. 发明授权

US09196688B2 Delamination and crack prevention in III-nitride wafers 有权
标题翻译： III型氮化物晶片的分层和防裂
公开(公告)号：US09196688B2
公开(公告)日：2015-11-24
申请号：US14191910
申请日：2014-02-27
申请人： International Rectifier Corporation
发明人： Michael A. Briere
IPC分类号： H01L29/15 , H01L29/20 , H01L21/78
CPC分类号： H01L21/0254 , H01L21/02002 , H01L21/02373 , H01L21/02378 , H01L21/02381 , H01L21/0242 , H01L21/02422 , H01L21/02538 , H01L21/30604 , H01L21/78 , H01L23/562 , H01L29/2003 , H01L2924/0002 , H01L2924/00
摘要： In an exemplary implementation, a method includes growing a III-Nitride body over a group IV substrate in a semiconductor wafer. The method includes forming at least one device layer over the III-Nitride body. The method also includes etching grid array trenches in the III-Nitride body, where the etching of the grid array trenches may extend into the group IV substrate. The method can also include forming an edge trench around a perimeter of the semiconductor wafer. The method further includes forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches.
摘要翻译：在示例性实施方式中，一种方法包括在半导体晶片中的IV族衬底上生长III-氮化物体。该方法包括在III-氮化物体上形成至少一个器件层。该方法还包括蚀刻III-氮化物体中的栅格阵列沟槽，其中栅极阵列沟槽的蚀刻可以延伸到IV族衬底中。该方法还可以包括在半导体晶片的周边周围形成边缘沟槽。该方法还包括通过沿着栅格阵列沟槽切割半导体晶片来形成单独的管芯。

83. 发明申请

US20150325566A1 Composite Device with Integrated Diode 有权
标题翻译：具有集成二极管的复合器件
公开(公告)号：US20150325566A1
公开(公告)日：2015-11-12
申请号：US14794370
申请日：2015-07-08
申请人： International Rectifier Corporation
发明人： Michael A. Briere
IPC分类号： H01L27/02 , H01L27/06 , H01L29/16 , H01L29/868 , H01L23/522 , H01L23/532 , H01L29/861 , H01L29/778 , H01L29/20
CPC分类号： H01L27/0255 , H01L21/8258 , H01L23/5226 , H01L23/53228 , H01L23/53257 , H01L23/53271 , H01L27/0605 , H01L27/0629 , H01L27/0688 , H01L29/1087 , H01L29/16 , H01L29/20 , H01L29/2003 , H01L29/41766 , H01L29/778 , H01L29/7786 , H01L29/7787 , H01L29/861 , H01L29/8613 , H01L29/868 , H01L2224/48091 , H01L2924/12032 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： There are disclosed herein various implementations of composite semiconductor devices. In one implementation, such a composite semiconductor device includes a transition body formed over a diode, the transition body including more than one semiconductor layer. The composite semiconductor device also includes a transistor formed over the transition body. The diode may be connected across the transistor using through-semiconductor vias, external electrical connectors, or a combination of the two.
摘要翻译：这里公开了复合半导体器件的各种实现方式。在一个实施方案中，这种复合半导体器件包括形成在二极管上的过渡体，所述过渡体包括多于一个的半导体层。复合半导体器件还包括形成在过渡体上的晶体管。二极管可以使用贯穿半导体通孔，外部电连接器或两者的组合跨越晶体管连接。

84. 发明授权

US09105566B2 Monolithic integrated composite group III-V and group IV device 有权
标题翻译：单片综合复合组III-V和IV组装置
公开(公告)号：US09105566B2
公开(公告)日：2015-08-11
申请号：US13968840
申请日：2013-08-16
申请人： International Rectifier Corporation
发明人： Michael A. Briere
IPC分类号： H01L21/02 , H01L29/205 , H01L21/8252 , H01L27/06 , H01L29/267 , H01L21/761
CPC分类号： H01L29/205 , H01L21/761 , H01L21/8252 , H01L27/0605 , H01L29/267
摘要： According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a sidewall of the trench.
摘要翻译：根据一个公开的实施例，一种用于制造单片集成复合器件的方法包括在IV族半导体衬底上形成III-V族半导体体，在III-V族半导体体中形成沟槽，并形成IV族半导体体在沟里。该方法还包括在IV族半导体本体中制造至少一种IV族半导体器件，并且在III-V族半导体器件中制造至少一种III-V族III族半导体器件。在一个实施例中，该方法还包括使III-V半导体体的上表面和IV族半导体本体的上表面平坦化，以使这些相应的上表面基本上共面。在一个实施例中，该方法还包括在与沟槽的侧壁相邻的所述IV族半导体主体的缺陷区域中制造至少一个无源器件。

85. 发明申请

US20150155358A1 Group III-V Transistor with Semiconductor Field Plate 有权
标题翻译：具有半导体场板的III-V族晶体管
公开(公告)号：US20150155358A1
公开(公告)日：2015-06-04
申请号：US14531181
申请日：2014-11-03
申请人： International Rectifier Corporation
发明人： Michael A. Briere
IPC分类号： H01L29/40 , H01L29/20 , H01L29/778
CPC分类号： H01L29/405 , H01L29/2003 , H01L29/7786 , H01L29/7787
摘要： There are disclosed herein various implementations of a group III-V transistor with a semiconductor field plate. Such a group III-V transistor includes a group III-V heterostructure situated over a substrate and configured to produce a two-dimensional electron gas (2DEG). In addition, the group III-V transistor includes a source electrode, a drain electrode, and a gate situated over the group heterostructure. The group III-V transistor also includes an insulator layer over the group III-V heterostructure and situated between the gate and the drain electrode, and a semiconductor field plate situated between the gate and the drain electrode, over the insulator layer.
摘要翻译：在此公开了具有半导体场板的III-V族晶体管的各种实现方式。这种III-V族晶体管包括位于衬底上并被配置为产生二维电子气（2DEG）的III-V族异质结构。此外，III-V族晶体管包括源电极，漏电极和位于组异质结构上的栅极。 III-V族晶体管还包括在III-V族异质结构之上并且位于栅极和漏极之间的绝缘体层，以及位于绝缘体层之上的位于栅极和漏极之间的半导体场板。

86. 发明授权

US08865575B2 Fabrication of III-nitride semiconductor device and related structures 有权
标题翻译： III族氮化物半导体器件及相关结构的制备
公开(公告)号：US08865575B2
公开(公告)日：2014-10-21
申请号：US14135425
申请日：2013-12-19
申请人： International Rectifier Corporation
发明人： Robert Beach , Michael A. Briere , Paul Bridger
IPC分类号： H01L21/20 , H01L21/36 , H01L21/02 , H01L29/66 , H01L29/778 , H01L29/20
CPC分类号： H01L21/0254 , H01L21/02378 , H01L21/02381 , H01L21/0242 , H01L21/02425 , H01L21/02458 , H01L21/02502 , H01L21/02507 , H01L21/0262 , H01L21/02631 , H01L29/2003 , H01L29/66462 , H01L29/7787
摘要： A method of fabricating a III-nitride power semiconductor device that includes growing a transition layer over a substrate using at least two distinct and different growth methods.
摘要翻译：一种制造III族氮化物功率半导体器件的方法，其包括使用至少两种截然不同的生长方法在衬底上生长过渡层。

87. 发明申请

US20140253217A1 RF Switch Gate Control 审中-公开
标题翻译：射频开关门控制
公开(公告)号：US20140253217A1
公开(公告)日：2014-09-11
申请号：US14195511
申请日：2014-03-03
申请人： International Rectifier Corporation
发明人： Michael A. Briere
IPC分类号： H03K17/16
CPC分类号： H03K17/162 , H03K17/693 , H03K2017/066 , H03K2217/0054
摘要： In one implementation, a switching circuit includes a pass switch including group III-V, for example III-Nitride, transistors coupled between an input of the switching circuit and an output of the switching circuit. The switching circuit further includes a shunt switch configured to ground the input of the switching circuit while the pass switch is disabled. The switching circuit also includes a gate control transistor configured to reduce resistance between a control terminal of the pass switch and/or the shunt switch and gate of the group III-V transistor of the pass switch and/or the shunt switch so as to enable and disable the pass switch and/or shunt switch. The gate control transistor can be coupled across a gate resistor of the pass switch and/or the shunt switch. The gate control transistor can reduce the resistance in order to lower the OFF state impedance of the pass switch and/or the shunt switch.
摘要翻译：在一个实施方案中，开关电路包括通过开关，其包括III-V族，例如III-Nitride，耦合在开关电路的输入端和开关电路的输出端之间的晶体管。开关电路还包括分路开关，其配置成在通路开关被禁用时将开关电路的输入接地。开关电路还包括栅极控制晶体管，其被配置为减小通路开关的控制端和/或并联开关与通过开关和/或并联开关的III-V晶体管的栅极之间的电阻，以使能并禁用通过开关和/或分流开关。栅极控制晶体管可以跨过通路开关和/或并联开关的栅极电阻耦合。栅极控制晶体管可以减小电阻以降低通路开关和/或并联开关的OFF状态阻抗。

88. 发明申请

US20140225162A1 Integrated Half-Bridge Circuit with Low Side and High Side Composite Switches 有权
标题翻译：集成半桥电路与低侧和高侧复合开关
公开(公告)号：US20140225162A1
公开(公告)日：2014-08-14
申请号：US14168926
申请日：2014-01-30
申请人： INTERNATIONAL RECTIFIER CORPORATION
发明人： Michael A. Briere
IPC分类号： H01L27/06
CPC分类号： H01L27/0623 , H01L21/8252 , H01L21/8258 , H01L27/0605 , H01L27/0688 , H01L27/0694 , H01L27/085 , H01L27/0883 , H01L2224/48091 , H01L2224/48145 , H01L2924/13091 , H02M3/337 , H03K17/107 , H03K17/567 , H03K2017/6875 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： There are disclosed herein various implementations of an integrated half-bridge circuit with low side and high side composite switches. In one exemplary implementation, such an integrated half-bridge circuit includes a III-N body including first and second III-N field-effect transistors (FETs) monolithically integrated with and situated over a first group IV FET. The integrated half-bridge circuit also includes a second group IV FET stacked over the III-N body. The first group IV FET is cascoded with the first III-N FET to provide one of the low side and the high side composite switches, and the second group IV FET is cascoded with the second III-N FET to provide the other of the low side and the high side composite switches. The first and second III-N FETs are normally ON FETs, and the low side composite switch and the high side composite switch are normally OFF switches
摘要翻译：这里公开了具有低侧和高侧复合开关的集成半桥电路的各种实施方式。在一个示例性实施方案中，这种集成半桥电路包括III-N体，其包括与第一组IV FET单片集成并位于第一组IV FET之上的第一和第二III-N场效应晶体管（FET）。集成半桥电路还包括堆叠在III-N体上的第二组IV FET。第一组IV FET与第一III-N FET串联以提供低侧和高侧复合开关之一，并且第二组IV FET与第二III-N FET级联以提供另一个低侧和高侧复合开关。第一和第二III-N FET通常为ON FET，低压复合开关和高侧复合开关通常为OFF开关

89. 发明申请

US20140203295A1 INTEGRATED POWER DEVICE WITH III-NITRIDE HALF BRIDGES 有权
标题翻译：集成功率器件与III-NITRIDE HALF BRIDGES
公开(公告)号：US20140203295A1
公开(公告)日：2014-07-24
申请号：US14222332
申请日：2014-03-21
申请人： International Rectifier Corporation
发明人： Michael A. Briere
IPC分类号： H01L29/778 , H01L29/205 , H01L29/20
CPC分类号： H01L29/7787 , H01L27/0605 , H01L29/2003 , H01L29/205 , H01L29/41758 , H01L29/778
摘要： A semiconductor device that includes a plurality of isolated half-bridges formed in a common semiconductor die.
摘要翻译：一种半导体器件，包括形成在公共半导体管芯中的多个隔离半桥。

90. 发明申请

US20140192441A1 DC/DC Converter with III-Nitride Switches 有权
标题翻译：具有III-Nitride开关的DC / DC转换器
公开(公告)号：US20140192441A1
公开(公告)日：2014-07-10
申请号：US14210151
申请日：2014-03-13
申请人： International Rectifier Corporation
发明人： Michael A. Briere , Jason Zhang , Bo Yang
IPC分类号： H02H7/12
CPC分类号： H02H7/1213 , H02M1/32 , H02M3/1588 , Y02B70/1466 , Y02B70/1483
摘要： Disclosed is a buck converter for converting a high voltage at the input of the buck converter to a low voltage at the output of the buck converter. The buck converter includes a control circuitry configured to control a duty cycle of a control switch, the control switch being interposed between the input and the output of the buck converter.A synchronous switch is interposed between the output and ground. The control switch and the synchronous switch comprise depletion-mode III-nitride transistors. In one embodiment, at least one of the control switch and the synchronous switches comprises a depletion-mode GaN HEMT. The buck converter further includes protection circuitry configured to disable current conduction through the control switch while the control circuitry is not powered up.
摘要翻译：公开了一种降压转换器，用于将降压转换器的输入处的高电压转换为降压转换器的输出处的低电压。降压转换器包括配置成控制控制开关的占空比的控制电路，控制开关插入降压转换器的输入和输出之间。同步开关插在输出和地之间。控制开关和同步开关包括耗尽型III族氮化物晶体管。在一个实施例中，控制开关和同步开关中的至少一个包括耗尽型GaN HEMT。降压转换器还包括保护电路，其被配置为在控制电路未上电时禁止通过控制开关的电流传导。

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