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    • 81. 发明授权
    • Pixel structure and thin film transistor
    • 像素结构和薄膜晶体管
    • US08835929B2
    • 2014-09-16
    • US13858090
    • 2013-04-07
    • AU Optronics Corp.
    • Peng-Bo XiYu-Chi Chen
    • H01L29/04H01L29/10H01L29/786H01L27/06H01L27/12
    • H01L27/1255H01L27/0629H01L27/12H01L27/1225H01L29/786
    • A pixel structure including a first thin film transistor (TFT), a second TFT and a storage capacitor is provided. The source electrode of the first TFT is connected to the gate electrode of the second TFT, and the semiconductor layer of the second TFT protrudes out two opposite side of the gate electrode of the second TFT. A thin film transistor including a gate electrode, a capacitance compensation structure, a semiconductor layer, a dielectric layer, a drain electrode and a source electrode is also provided. The capacitance compensation structure is electrically connected to the gate electrode. The semiconductor layer partially overlaps the gate electrode, and extends to overlap the capacitance compensation structure.
    • 提供了包括第一薄膜晶体管(TFT),第二TFT和存储电容器的像素结构。 第一TFT的源电极连接到第二TFT的栅电极,第二TFT的半导体层从第二TFT的栅电极的两相对侧突出。 还提供了包括栅电极,电容补偿结构,半导体层,电介质层,漏电极和源电极的薄膜晶体管。 电容补偿结构电连接到栅电极。 半导体层与栅电极部分重叠,并延伸以与电容补偿结构重叠。
    • 82. 发明授权
    • Image sensor formed by silicon rich oxide material
    • 由富硅氧化物材料形成的图像传感器
    • US08835829B2
    • 2014-09-16
    • US13671541
    • 2012-11-07
    • AU Optronics Corp.
    • Ming-Hung Chuang
    • H01J40/14H01L27/00H01L27/146H04N5/374H04N5/3745
    • H01L27/14609H04N5/3741H04N5/3745
    • An image sensor includes a light-sensing element, a first transistor, and a second transistor. The light-sensing element has a first end and a second end electrically connected to a select line. The first transistor has a first end electrically connected to a first control line, a control end electrically connected to the first end, and a second end electrically connected to the first end of the light-sensing element. The second transistor has a first end electrically connected to a voltage source, a control end electrically connected to the first end of the light-sensing element, and a second end electrically connected to an output line. The light-sensing element uses the material of silicon rich oxide so that the light-sensing element can sense the luminance variance and have the characteristic of the capacitor for the level boost.
    • 图像传感器包括光感测元件,第一晶体管和第二晶体管。 光感测元件具有电连接到选择线的第一端和第二端。 第一晶体管具有电连接到第一控制线的第一端,与第一端电连接的控制端,以及电连接到光感测元件的第一端的第二端。 第二晶体管具有电连接到电压源的第一端,与光感测元件的第一端电连接的控制端,以及电连接到输出线的第二端。 感光元件使用富硅氧化物的材料,使得感光元件可以感测亮度方差,并具有用于电平提升的电容器的特性。
    • 83. 发明申请
    • DISPLAY DEVICE AND COMMON VOLTAGE GENERATOR THEREOF
    • 显示设备及其通用电压发生器
    • US20140252964A1
    • 2014-09-11
    • US14140885
    • 2013-12-26
    • AU OPTRONICS CORP.
    • Ming-Hung WUCheng-Chiu PAI
    • G09G3/22H03K19/0175
    • H03K19/0175G09G3/3655
    • A voltage generator includes a latch and a first voltage adjustment circuit. The latch includes a latch input terminal, a trigger terminal, a positive latch output terminal and a negative latch output terminal. The latch is configured to have the latch input terminal thereof for receiving an input signal, the trigger terminal thereof for receiving a trigger signal, the positive latch output terminal thereof for outputting a first latch output signal having a phase same as that of the input signal, and the negative latch output terminal thereof for outputting a second latch output signal having a phase opposite to that of the input signal. The first voltage adjustment circuit is electrically coupled to the latch and configured to output a first common voltage signal. A display device using the aforementioned voltage generator is also provided.
    • 电压发生器包括闩锁和第一电压调节电路。 锁存器包括锁存器输入端子,触发端子,正锁存器输出端子和负锁存器输出端子。 锁存器被配置为具有用于接收输入信号的锁存器输入端,其触发端用于接收触发信号,其正锁存输出端用于输出与输入信号的相位相同的第一锁存输出信号 ,及其负锁存输出端,用于输出具有与输入信号相反的相位的第二锁存输出信号。 第一电压调节电路电耦合到锁存器并且被配置为输出第一公共电压信号。 还提供了使用上述电压发生器的显示装置。
    • 84. 发明授权
    • Blocking element and its use in protective structure
    • 阻塞元件及其在保护结构中的应用
    • US08820527B2
    • 2014-09-02
    • US13633607
    • 2012-10-02
    • AU Optronics Corp.
    • Tai-Ling ChanChung-Yu MaoChung-Kuan Ting
    • B65D85/48B65D81/02
    • B65D81/055Y10T428/1376Y10T428/24479Y10T428/24504
    • The disclosure provides a blocking element and its use in a protective structure. The blocking element includes a base and a first blocking plate. The base includes a surface and a recession formed downwardly towards the surface. The first blocking plate is connected to a first cross-connect part of the recession. The first blocking plate is used for pivoting on the first cross-connect part and includes a first blocking position and a first closing position in relative to the first cross-connect part. When the first blocking plate is at the first blocking position, a first blocking part of the first blocking plate protrudes from the surface. When the first blocking plate is pressed towards the recession to the first closing position by an external force, at least one portion of the first blocking part is contained in the recession.
    • 本公开提供了阻挡元件及其在保护结构中的用途。 阻挡元件包括基部和第一阻挡板。 底座包括朝向表面向下形成的表面和凹陷。 第一挡板连接到经济衰退的第一交叉连接部分。 第一阻挡板用于在第一交叉连接部分上枢转并且包括相对于第一交叉连接部分的第一阻挡位置和第一关闭位置。 当第一阻挡板处于第一阻挡位置时,第一阻挡板的第一阻挡部分从表面突出。 当第一阻挡板通过外力朝向第一闭合位置的凹陷部被按压时,第一阻挡部件的至少一部分被包含在凹陷中。
    • 85. 发明申请
    • LEVEL SHIFT CIRCUIT AND DRIVING METHOD THEREOF
    • 水平移位电路及其驱动方法
    • US20140240307A1
    • 2014-08-28
    • US13863390
    • 2013-04-16
    • AU OPTRONICS CORP.
    • Yun-Chi ChenYueh-Han LiHuang-Ti LinMing-Sheng Lai
    • G09G5/12
    • G09G5/12G09G3/3696G09G2310/08
    • A level shift circuit includes an input end, a decoding circuit, a control circuit, and a plurality of output circuits. The input end is configured to receive a coded signal string including a starting code, a setting code, a clock standard signal and an ending code. The decoding circuit is coupled to the input end for decoding the coded signal string and outputting the starting code, the setting code, the clock standard signal and the ending code respectively. The control circuit is coupled to the decoding circuit for controlling logic levels of a plurality of logic driving signals according to the setting code and the clock standard signal after receiving the starting code, and stopping changing the logic driving signals after receiving the ending code. The plurality of output circuits are coupled to the control circuit for outputting a plurality of clock signals according to the corresponding logic driving circuit.
    • 电平移位电路包括输入端,解码电路,控制电路和多个输出电路。 输入端被配置为接收包括起始码,设定码,时钟标准信号和结束码的编码信号串。 解码电路耦合到输入端,用于解码编码信号串,分别输出起始码,设定码,时钟标准信号和结束码。 控制电路耦合到解码电路,用于在接收到起始码之后根据设定码和时钟标准信号控制多个逻辑驱动信号的逻辑电平,并且在接收到结束码之后停止改变逻辑驱动信号。 多个输出电路耦合到控制电路,用于根据对应的逻辑驱动电路输出多个时钟信号。
    • 87. 发明授权
    • Shift register
    • 移位寄存器
    • US08811567B2
    • 2014-08-19
    • US13771042
    • 2013-02-19
    • AU Optronics Corp.
    • Chen-Yi WuTa-Wen Liao
    • G11C19/00G11C19/28
    • G11C19/00G11C19/28
    • A shift register for providing a plurality of gate signals includes an Nth stage shift register unit and an (N+1)th stage shift register unit. The Nth stage shift register unit includes a first pull up unit, a first driving unit, a first control unit and a first auxiliary pull down unit. The (N+1)th stage shift register unit includes a second pull up unit, a second driving unit, a first pull down unit and a second auxiliary pull down unit. The first and second pull up units are both coupled to the first and second driving units for controlling the first and second driving units to generate gate signals. The first and second auxiliary pull down units are both coupled to the first control unit for pulling down the gate signals.
    • 用于提供多个门信号的移位寄存器包括第N级移位寄存器单元和第(N + 1)级移位寄存器单元。 第N级移位寄存器单元包括第一上拉单元,第一驱动单元,第一控制单元和第一辅助下拉单元。 第(N + 1)级移位寄存器单元包括第二上拉单元,第二驱动单元,第一下拉单元和第二辅助下拉单元。 第一和第二上拉单元都耦合到第一和第二驱动单元,用于控制第一和第二驱动单元以产生门信号。 第一和第二辅助下拉单元都耦合到第一控制单元以用于下拉栅极信号。
    • 89. 发明申请
    • PIXEL UNIT AND PIXEL ARRAY
    • 像素单元和像素阵列
    • US20140209932A1
    • 2014-07-31
    • US13969618
    • 2013-08-19
    • AU Optronics Corp.
    • Chih-Hsuan Huang
    • H01L27/12
    • H01L27/124G02F1/13624G02F2001/134345
    • A pixel array and a pixel unit thereof adapted in a display panel are provided. The pixel array includes a plurality of pixel units, and each pixel unit includes a first gate line, a second gate line, a data line, a first sub-pixel, a second sub-pixel and a third sub-pixel. The first sub-pixel is electrically connected to the second gate line and electrically connected to the data line through the third sub-pixel. The second sub-pixel is electrically connected to the second gate line and the data line. The third sub-pixel is electrically connected to the first gate line and the data line.
    • 提供了适用于显示面板的像素阵列及像素单元。 像素阵列包括多个像素单元,并且每个像素单元包括第一栅极线,第二栅极线,数据线,第一子像素,第二子像素和第三子像素。 第一子像素电连接到第二栅极线并且通过第三子像素电连接到数据线。 第二子像素电连接到第二栅极线和数据线。 第三子像素电连接到第一栅极线和数据线。