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81. 发明授权

US09136181B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09136181B2
公开(公告)日：2015-09-15
申请号：US14355919
申请日：2012-12-07
申请人： Institute of Microelectronics, Chinese Academy of Sciences
发明人： Qiuxia Xu , Huilong Zhu , Gaobo Xu , Huajie Zhou , Dapeng Chen
IPC分类号： H01L21/8238 , H01L29/78 , H01L29/49 , H01L29/51 , H01L21/02 , H01L21/266 , H01L21/28 , H01L21/3105 , H01L21/321 , H01L21/3213 , H01L21/324 , H01L29/167 , H01L29/423 , H01L29/66
CPC分类号： H01L21/823857 , H01L21/0228 , H01L21/0254 , H01L21/266 , H01L21/28141 , H01L21/28176 , H01L21/31051 , H01L21/3212 , H01L21/3213 , H01L21/324 , H01L21/823842 , H01L29/167 , H01L29/42364 , H01L29/42372 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/78
摘要： A method for manufacturing a semiconductor device, comprising: defining an active region on the semiconductor substrate; forming an interfacial oxide layer on a surface of the semiconductor substrate; forming a high-K gate dielectric on the interfacial oxide layer; forming a first metal gate layer on the high-K gate dielectric; forming a dummy gate layer on the first metal gate layer; patterning the dummy gate layer, the first metal gate layer, the high-K gate dielectric and the interfacial oxide layer to form a gate stack structure; forming a gate spacer surrounding the gate stack structure; forming S/D regions for NMOS and PMOS respectively; depositing interlayer dielectric and planarization by CMP to expose the surface of dummy gate layer; removing the dummy gate layer so as to form a gate opening; implanting dopant ions into the first metal gate layer; forming a second metal gate layer on the first metal gate layer so as to fill the gate opening; and performing annealing, so that the dopant ions diffuse and accumulate at an upper interface between the high-K gate dielectric and the first metal gate layer and at a lower interface between the high-K gate dielectric and the interfacial oxide layer, and electric dipoles are generated by interfacial reaction at the lower interface between the high-K gate dielectric and the interfacial oxide layer.
摘要翻译：一种制造半导体器件的方法，包括：在所述半导体衬底上限定有源区; 在所述半导体衬底的表面上形成界面氧化物层; 在界面氧化物层上形成高K栅电介质; 在高K栅极电介质上形成第一金属栅极层; 在所述第一金属栅极层上形成伪栅极层; 图案化虚拟栅极层，第一金属栅极层，高K栅极电介质和界面氧化物层以形成栅极堆叠结构; 形成围绕所述栅堆叠结构的栅极间隔; 分别形成NMOS和PMOS的S / D区域; 通过CMP沉积层间电介质和平面化以暴露虚拟栅极层的表面; 去除虚拟栅极层以形成栅极开口; 将掺杂剂离子注入第一金属栅极层; 在所述第一金属栅极层上形成第二金属栅极层以填充所述栅极开口; 并执行退火，使得掺杂剂离子在高K栅极电介质和第一金属栅极层之间以及高K栅极电介质和界面氧化物层之间的下界面处的上界面处扩散并积聚，并且电偶极子通过界面反应在高K栅极电介质和界面氧化物层之间的下界面产生。

82. 发明授权

US09136160B2 Solid hole array and method for forming the same 有权
标题翻译：固体孔阵列及其形成方法
公开(公告)号：US09136160B2
公开(公告)日：2015-09-15
申请号：US13697372
申请日：2012-07-31
申请人： Lijun Dong , Chao Zhao
发明人： Lijun Dong , Chao Zhao
IPC分类号： H01L23/498 , H01L21/768 , H01L23/14 , H01L21/48
CPC分类号： H01L21/76802 , H01L21/486 , H01L23/147 , H01L23/49827 , H01L2924/0002 , H01L2924/00
摘要： A solid hole array and a method for forming the same are disclosed. The solid hold array may comprise: substrate with a via; a top hole array base formed on a top surface of the substrate and a bottom hole array base formed on a bottom surface of the substrate, wherein a front hole is located in the top hole array base at a place corresponding to the via; and top protection layer formed on a surface and sidewalls of the top hole array base and a bottom protection layer formed on a surface of the bottom hole array base, wherein a rear window is located in the bottom hole array base and the bottom protection layer at a place corresponding to the via.
摘要翻译：公开了一种固体孔阵列及其形成方法。固体保持阵列可以包括：具有通孔的基底; 形成在所述基板的上表面上的顶孔阵列基座和形成在所述基板的底面的底孔阵列基座，其中，在与所述通孔相对应的位置处，所述顶孔阵列基座中的前孔位于所述顶孔阵列基底中; 以及形成在顶孔阵列基底的表面和侧壁上的顶部保护层和形成在底部孔阵列基底的表面上的底部保护层，其中后部窗口位于底部孔阵列基底中，底部保护层位于底部保护层一个对应于通道的地方。

83. 发明授权

US09117926B2 Semiconductor devices and methods for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US09117926B2
公开(公告)日：2015-08-25
申请号：US14144275
申请日：2013-12-30
申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
发明人： Huilong Zhu , Qingqing Liang
IPC分类号： H01L21/8234 , H01L27/088 , H01L21/8238 , H01L29/66
CPC分类号： H01L21/823437 , H01L21/823456 , H01L21/823462 , H01L21/823468 , H01L21/823493 , H01L21/82385 , H01L27/088 , H01L29/66545 , H01L29/66553
摘要： A semiconductor device and a method of manufacturing the same is disclosed. In one aspect, the method comprises forming a first MOSFET having a first gate length in a semiconductor substrate, and forming a second MOSFET having a second gate length in the semiconductor substrate. Furthermore, the second gate length is less than the first gate length, and wherein the second MOSFET has a gate stack in the form of a spacer having a gate conductor and a gate dielectric isolating the gate conductor from the semiconductor substrate.
摘要翻译：公开了一种半导体器件及其制造方法。在一个方面，该方法包括在半导体衬底中形成具有第一栅极长度的第一MOSFET，并在半导体衬底中形成具有第二栅极长度的第二MOSFET。此外，第二栅极长度小于第一栅极长度，并且其中第二MOSFET具有隔离栅形式的栅极叠层，该栅极叠层具有栅极导体和将栅极导体与半导体衬底隔离的栅极电介质。

84. 发明授权

US09070744B2 Shallow trench isolation structure, manufacturing method thereof and a device based on the structure 有权
标题翻译：浅沟槽隔离结构，其制造方法和基于该结构的器件
公开(公告)号：US09070744B2
公开(公告)日：2015-06-30
申请号：US13519573
申请日：2011-08-03
申请人： Jiang Yan
发明人： Jiang Yan
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76232
摘要： The present invention relates to a shallow trench isolation structure, manufacturing method thereof and a device based on the structure. The present invention provides a method for manufacturing a shallow trench isolation (STI) structure, characterized in comprising the following steps: providing a semiconductor substrate; forming an insulating medium on said semiconductor substrate; etching a part of the insulating medium by using a mask to expose the semiconductor substrate thereunder, the unetched insulating medium forming STI regions; and epitaxially growing a semiconductor layer on said semiconductor substrate between said STI regions as an active region. With the method provided by the present invention, the problem of filling a small-size trench is solved and the problem of STI step height is overcome.
摘要翻译：本发明涉及一种浅沟槽隔离结构，其制造方法和基于该结构的器件。本发明提供一种制造浅沟槽隔离（STI）结构的方法，其特征在于包括以下步骤：提供半导体衬底; 在所述半导体衬底上形成绝缘介质; 通过使用掩模蚀刻绝缘介质的一部分以暴露其下的半导体衬底，形成STI区的未蚀刻绝缘介质; 并且在所述STI区域之间的所述半导体衬底上外延生长半导体层作为有源区。利用本发明提供的方法，解决了填充小尺寸沟槽的问题，克服了STI步长的问题。

85. 发明申请

US20150171186A1 SEMICONDUCTOR DEVICE MANUFACTURING METHOD 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：US20150171186A1
公开(公告)日：2015-06-18
申请号：US14413697
申请日：2012-07-31
申请人： Haizhou Yin , Huilong Zhu
发明人： Haizhou Yin , Huilong Zhu
IPC分类号： H01L29/66 , H01L21/311 , H01L21/3105 , H01L29/45 , H01L21/3205 , H01L29/417 , H01L21/02
CPC分类号： H01L29/6659 , H01L21/02532 , H01L21/0257 , H01L21/31053 , H01L21/31111 , H01L21/31144 , H01L21/32053 , H01L29/41783 , H01L29/45 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/7834 , H01L29/7835
摘要： The present application discloses a method for manufacturing a semiconductor device, comprising: forming a gate stack structure and gate sidewall spacers on the substrate, and forming a source region and a drain region on the substrate on opposite sides of the gate stack structure and the gate sidewall spacers, respectively; selectively forming a block layer in the drain region, wherein the block layer covers the drain region and exposes the source region; epitaxially forming an raised source region in the exposed source region; removing the block layer. According to the semiconductor device manufacturing method in the present disclosure, by selectively forming an raised source region in the source region side to form an asymmetric device structure, the parasitic resistance on the source region side and the parasitic capacitance on the drain region side are pertinently reduced and the device performance is effectively improved.
摘要翻译：本申请公开了一种用于制造半导体器件的方法，包括：在衬底上形成栅极叠层结构和栅极侧壁间隔物，并且在栅极堆叠结构和栅极的相对侧上在衬底上形成源极区域和漏极区域侧壁间隔件; 在所述漏极区中选择性地形成阻挡层，其中所述阻挡层覆盖所述漏极区并暴露所述源极区; 在所述暴露的源区中外延地形成凸起的源区; 去除块层。根据本公开的半导体器件制造方法，通过在源极区侧选择性地形成凸起的源极区域以形成非对称的器件结构，源极侧的寄生电阻和漏极区侧的寄生电容是相关的降低了设备性能，有效地提高了设备性能。

86. 发明申请

US20150145046A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20150145046A1
公开(公告)日：2015-05-28
申请号：US14397586
申请日：2012-05-22
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L27/12 , H01L29/66 , H01L21/266 , H01L21/02 , H01L21/306 , H01L21/308 , H01L21/768 , H01L29/78 , H01L21/84
CPC分类号： H01L27/1203 , H01L21/02529 , H01L21/02532 , H01L21/2652 , H01L21/266 , H01L21/30604 , H01L21/3081 , H01L21/743 , H01L21/76897 , H01L21/84 , H01L29/165 , H01L29/66636 , H01L29/66659 , H01L29/66772 , H01L29/78 , H01L29/78612 , H01L29/78648
摘要： The present invention provides a method for manufacturing a semiconductor structure, which comprises following steps: providing a substrate, which comprises upwards in order a base layer, a buried isolation layer, a buried ground layer, an ultra-thin insulating buried layer and a surface active layer; implementing ion implantation doping to the buried ground layer; forming a gate stack, sidewall spacers and source/drain regions on the substrate; forming a mask layer on the substrate that covers the gate stack and the source/drain regions, and etching the mask layer to expose the source region; etching the source region and the ultra-thin insulating buried layer under the source region to form an opening that exposes the buried ground layer; filling the opening through epitaxial process to form a contact plug for the buried ground layer. Accordingly, the present invention further provides a semiconductor structure. The present invention proposes formation of a buried ground layer contact plug, which thence connects buried ground layer electrically to source region, thereby enhancing control capabilities of a semiconductor device over threshold voltages, suppressing short-channel effects and improving device performance; whereas no independent contact is required to build for the buried ground layer, which thence saves device area and simplifies manufacturing process accordingly.
摘要翻译：本发明提供了一种制造半导体结构的方法，其包括以下步骤：提供基底，其基本层向上依次包括掩埋隔离层，埋地层，超薄绝缘掩埋层和表面活性层对埋地层进行离子注入掺杂; 在衬底上形成栅极堆叠，侧壁间隔物和源极/漏极区域; 在覆盖栅极堆叠和源极/漏极区域的衬底上形成掩模层，并蚀刻掩模层以暴露源极区域; 蚀刻源极区域下的源极区域和超薄绝缘掩埋层，形成暴露埋入地层的开口; 通过外延工艺填充开口以形成埋地层的接触塞。因此，本发明还提供一种半导体结构。本发明提出一种掩埋地层接触塞的形成，其将掩埋地层电连接到源极区域，从而提高半导体器件在阈值电压下的控制能力，抑制短沟道效应和提高器件性能; 而不需要独立的接触来构建埋地层，从而节省设备面积并相应地简化制造过程。

87. 发明授权

US09012965B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09012965B2
公开(公告)日：2015-04-21
申请号：US13379120
申请日：2011-04-22
申请人： Jun Luo , Chao Zhao
发明人： Jun Luo , Chao Zhao
IPC分类号： H01L29/76 , H01L29/47 , H01L29/66 , H01L29/78 , H01L21/285 , H01L21/265
CPC分类号： H01L29/47 , H01L21/26506 , H01L21/28518 , H01L29/66545 , H01L29/66643 , H01L29/7839
摘要： The invention discloses a novel MOSFET device fabricated by a gate last process and its implementation method, the device comprising: a substrate; a gate stack structure located on a channel region in the substrate, on either side of which is eliminated the conventional isolation spacer; an epitaxially grown ultrathin metal silicide constituting a source/drain region. Wherein the device eliminates the high resistance region below the conventional isolation spacer; a dopant segregation region with imlanted ions is formed between the source/drain and the channel region, which decreases the Schottky barrier height between the metal silicide source/drain and the channel. At the same time, the epitaxially grown metal silicide can withstand a second high-temperature annealing used for improving the performance of a high-k gate dielectric material, which further improves the performance of the device. The MOSFET according to the invention reduces the parasitic resistance and capacitance greatly and thereby decreases the RC delay, thus improving the switching performance of the MOSFET device significantly.
摘要翻译：本发明公开了一种通过门最后工艺制造的新型MOSFET器件及其实现方法，该器件包括：衬底; 栅极叠层结构位于衬底的沟道区上，其任一侧消除了传统隔离间隔物; 构成源极/漏极区域的外延生长的超薄金属硅化物。其中该器件消除了传统隔离间隔物下面的高电阻区域; 在源极/漏极和沟道区之间形成具有经过离子注入的掺杂剂偏析区域，这降低了金属硅化物源极/漏极与沟道之间的肖特基势垒高度。同时，外延生长的金属硅化物可以承受用于改善高k栅介质材料性能的第二高温退火，这进一步提高了器件的性能。根据本发明的MOSFET大大降低了寄生电阻和电容，从而降低了RC延迟，从而显着提高了MOSFET器件的开关性能。

88. 发明申请

US20150102416A1 DUAL-METAL GATE CMOS DEVICES AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：双金属门CMOS器件及其制造方法
公开(公告)号：US20150102416A1
公开(公告)日：2015-04-16
申请号：US14396845
申请日：2012-05-17
申请人： Huaxiang Yin , Zuozhen Fu , Qiuxia Xu , Dapeng Chen
发明人： Huaxiang Yin , Zuozhen Fu , Qiuxia Xu , Dapeng Chen
IPC分类号： H01L21/8234 , H01L29/51 , H01L27/092
CPC分类号： H01L21/28088 , H01L21/28 , H01L21/28008 , H01L21/28026 , H01L21/28044 , H01L21/28079 , H01L21/82345 , H01L21/823842 , H01L27/092 , H01L27/0928 , H01L29/517 , H01L29/66515 , H01L29/66545
摘要： A method for manufacturing a dual metal CMOS device comprising: forming a first type metal work function modulation layer in the first gate trench and the second gate trench; forming a second type work function metal diffusion source layer in the first gate trench and the second gate trench; forming a heat isolation layer that shields the region of the first type device; and thermally annealing the regions where the first type device and the second type device are located.
摘要翻译：一种用于制造双金属CMOS器件的方法，包括：在所述第一栅极沟槽和所述第二栅极沟槽中形成第一类型金属功函数调制层; 在所述第一栅极沟槽和所述第二栅极沟槽中形成第二类型功函数金属扩散源层; 形成屏蔽所述第一类型装置的区域的热隔离层; 并对第一类型器件和第二类型器件所在的区域进行热退火。

89. 发明授权

US09000409B2 3D semiconductor memory device and manufacturing method thereof 有权
标题翻译： 3D半导体存储器件及其制造方法
公开(公告)号：US09000409B2
公开(公告)日：2015-04-07
申请号：US13376276
申请日：2011-06-30
申请人： Zongliang Huo , Ming Liu
发明人： Zongliang Huo , Ming Liu
IPC分类号： H01L47/00 , H01L27/24 , H01L45/00
CPC分类号： H01L27/249 , H01L27/2454 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/147
摘要： The present application discloses a 3D semiconductor memory device having 1T1R memory configuration based on a vertical-type gate-around transistor, and a manufacturing method thereof. A on/off current ratio can be well controlled by changing a width and a length of a channel of the gate-around transistor, so as to facilitate multi-state operation of the 1T1R memory cell. Moreover, the vertical transistor has a smaller layout size than a horizontal transistor, so as to reduce the layout size effectively. Thus, the 3D semiconductor memory device can be integrated into an array with a high density.
摘要翻译：本申请公开了一种具有基于垂直型栅极晶体管的1T1R存储器配置的3D半导体存储器件及其制造方法。可以通过改变栅极周围晶体管的沟道的宽度和长度来良好地控制开/关电流比，以便于1T1R存储单元的多状态操作。此外，垂直晶体管具有比水平晶体管更小的布局尺寸，以便有效地减小布局尺寸。因此，3D半导体存储器件可以集成到具有高密度的阵列中。

90. 发明授权

US08999802B2 Method for manufacturing semiconductor device by selectively removing end portions of gate dielectric layer and then filling end portions with dielectric layer 有权
标题翻译：通过选择性地去除栅极电介质层的端部然后用电介质层填充端部来制造半导体器件的方法
公开(公告)号：US08999802B2
公开(公告)日：2015-04-07
申请号：US13813554
申请日：2012-07-30
申请人： Yunfei Liu , Haizhou Yin
发明人： Yunfei Liu , Haizhou Yin
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/31 , H01L21/469 , H01L29/66 , H01L21/265 , H01L21/28 , H01L29/78
CPC分类号： H01L29/66492 , H01L21/26513 , H01L21/26586 , H01L21/28158 , H01L29/6659 , H01L29/7833
摘要： A method for manufacturing a semiconductor device is disclosed. In one embodiment, the method comprises: forming a gate stack on a substrate, wherein the gate stack comprises a gate dielectric layer and a gate conductor layer; selectively etching end portions of the gate dielectric layer to form gaps; and filling a material for the gate dielectric layer into the gaps.
摘要翻译：公开了一种制造半导体器件的方法。在一个实施例中，该方法包括：在衬底上形成栅极堆叠，其中栅极叠层包括栅极介电层和栅极导体层; 选择性地蚀刻栅介质层的端部以形成间隙; 并将栅极电介质层的材料填充到间隙中。

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