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81. 发明申请

US20170163269A1 SYSTEMS AND METHOD INVOLVING FAST-ACQUISITION LOCK FEATURES ASSOCIATED WITH PHASE LOCKED LOOP CIRCUITRY 审中-公开
公开(公告)号：US20170163269A1
公开(公告)日：2017-06-08
申请号：US15442375
申请日：2017-02-24
申请人： GSI Technology, Inc.
发明人： Chao-Hung CHANG
IPC分类号： H03L7/087 , G11C19/00
CPC分类号： H03L7/0891 , H03L7/0807 , H03L7/087 , H03L7/089 , H03L7/0895 , H03L7/113
摘要： Systems and methods are disclosed relating to fields of clock/data acquisition or handling, such as clock/data locking and the like. In one exemplary implementation, phase lock loop (PLL) circuitry may comprise voltage controlled oscillator (VCO) circuitry, phase frequency detector, converting circuitry, and frequency detector (FD) circuitry that outputs a frequency difference signal proportional to frequency difference between frequencies of a feedback clock signal and a reference clock signal.

82. 发明授权

US09646714B2 Shift register, semiconductor device, display device, and electronic device 有权
公开(公告)号：US09646714B2
公开(公告)日：2017-05-09
申请号：US14800765
申请日：2015-07-16
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Atsushi Umezaki
IPC分类号： G11C19/00 , G11C19/18 , G09G3/3266 , G09G3/36
CPC分类号： G11C19/184 , G09G3/3266 , G09G3/3648 , G09G3/3677 , G09G2300/0426 , G09G2310/0267 , G09G2310/0275 , G09G2310/0286 , G09G2310/0289 , G09G2320/02 , G09G2320/043 , G09G2330/021 , G09G2330/023
摘要： The invention provides a semiconductor device and a shift register, in which low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire. One of a source and a drain of the third transistor is connected to a second wire, the other of the source and the drain thereof is connected to the gate electrode of the second transistor, and a gate electrode thereof is connected to a fourth wire. One of a source and a drain of the fourth transistor is connected to the second wire, the other of the source and the drain thereof is connected to the sixth wire, and a gate electrode thereof is connected to the fourth wire.

83. 发明申请

US20170125073A1 Affinity Data Collection in a Computing System 审中-公开
公开(公告)号：US20170125073A1
公开(公告)日：2017-05-04
申请号：US15399681
申请日：2017-01-05
申请人： KnuEdge Incorporated
发明人： Douglas A. Palmer , Jerome V. Coffin
IPC分类号： G11C7/10 , G11C19/00
CPC分类号： G06F11/3006 , G06F9/50 , G06F9/5011 , G06F9/5066 , G06F9/5088 , G06F11/3024 , G06F11/3409 , G06F2212/657 , G11C7/1036 , G11C19/00
摘要： A data collecting instrument including an input coupled with an output network port of a processing device, the input configured to receive a destination address of each data packet transmitted from the output network port, where the processing device is connected to a plurality of processing devices and is configured to transmit data packets from output network ports of the processing device to other devices of the plurality; one or more address registers configured to store information about a destination address range; a counter register configured to store a counter value; and digital circuitry coupled with the input, the one or more address registers, and the counter register; the digital circuitry configured to (i) determine, based on the information stored in the one or more address registers, that the destination address is within the destination address range; and (ii) increment the counter value stored in the counter register.

84. 发明授权

US09626890B2 Shift register and method of driving shift register 有权
公开(公告)号：US09626890B2
公开(公告)日：2017-04-18
申请号：US14803126
申请日：2015-07-20
申请人： AU Optronics Corp.
发明人： Wei-Li Lin , Che-Wei Tung , Chia-Heng Chen
IPC分类号： G11C19/00 , G09G3/20 , G11C19/28
CPC分类号： G09G3/20 , G09G2310/0267 , G09G2310/0286 , G09G2310/08 , G09G2320/0214 , G09G2320/0219 , G11C19/28
摘要： A shift register includes a plurality of stages of shift register circuit. Each stage of shift register circuit includes a first switch, an input circuit, a pull-down circuit, and a pull-down voltage regulator circuit. The first switch is used to output a scan signal according to a voltage level of a node and a clock signal. The input circuit is used to pull up the voltage level of the node according to a signal from a previous M-th stage of shift register circuit. The pull-down circuit is used to pull down the voltage level of the node according to the clock signal and a signal from a following L-th shift register circuit and reduce current leakage at the node. The pull-down voltage regulator circuit is used to pull down the voltage levels of the node and the scan signal according to the voltage level of the node.

85. 发明授权

US09590632B2 Pulse output circuit, shift register, and display device 有权
标题翻译：脉冲输出电路，移位寄存器和显示器件
公开(公告)号：US09590632B2
公开(公告)日：2017-03-07
申请号：US14702834
申请日：2015-05-04
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Shou Nagao , Munehiro Azami , Yoshifumi Tanada
IPC分类号： H03K19/096 , G09G3/36 , G11C19/00 , G11C19/28 , H03K19/017
CPC分类号： G09G3/3648 , G09G3/3614 , G09G3/3688 , G09G2300/0408 , G09G2300/0426 , G09G2310/0254 , G09G2310/0283 , G09G2310/0286 , G09G2310/0289 , G09G2310/0291 , G09G2310/0297 , G09G2310/08 , G11C19/00 , G11C19/28 , H01L2924/0002 , H03K19/01735 , H03K19/096 , H01L2924/00
摘要： A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD−V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD. When SP becomes low level; CK3 becomes low level; and CK1 becomes high level, the potential at the signal output section (Out) becomes low level again.
摘要翻译：提供一种电路，其由一种导电类型的TFT构成，并且能够输出正常振幅的信号。当输入时钟信号CK1变为高电平时，TFT（101,103）中的每一个导通以将信号输出部分（Out）处的电位置为低电平。然后将脉冲输入到信号输入部（In）并变为高电平。 TFT（102）的栅极电位增加到（VDD-V thN），栅极浮起来。 TFT（102）因此被导通。然后，CK1变为低电平，并且每个TFT（101,103）被关断。同时，CK3变为高电平，信号输出部分的电位增加。同时，通过电容器（104）的功能，TFT（102）的栅极处的电位增加到等于或高于（VDD + V thN）的电平，使得出现在信号输出部分（Out ）变为等于VDD。当SP变低时 CK3变低并且CK1变为高电平时，信号输出部（Out）的电位再次变为低电平。

86. 发明授权

US09589667B2 Gate drive circuit and drive method for the same 有权
标题翻译：门驱动电路及驱动方式相同
公开(公告)号：US09589667B2
公开(公告)日：2017-03-07
申请号：US14730164
申请日：2015-06-03
申请人： Shanghai Tianma Micro-Electronics Co., Ltd. , Tianma Micro-Electronics Co., Ltd.
发明人： Zhaokeng Cao , Tinghai Wang , Dandan Qin
IPC分类号： G11C19/00 , G11C19/28 , G09G3/20 , G09G3/36
CPC分类号： G11C19/287 , G09G3/20 , G09G3/3677 , G09G2300/0408 , G09G2310/0267 , G09G2310/0286 , G11C19/28
摘要： A gate drive circuit is disclosed. The drive circuit includes M cascaded shift registers, where M is a natural number, and a clock controller configured to generate two reverse-phase clock signals. The drive circuit also includes a high level controller configured to generate a high level signal, and a low level controller configured to generate a low level signal, where one of the high level controller and the low level controller is configured to generate an initial pulse signal during an initial stage. The drive circuit also includes a start unit cascaded with the M shift registers, where the start unit is configured to provide a start signal to the shift registers.
摘要翻译：公开了一种栅极驱动电路。驱动电路包括M级联移位寄存器，其中M是自然数，并且时钟控制器被配置为产生两个反相时钟信号。驱动电路还包括被配置为产生高电平信号的高电平控制器和被配置为产生低电平信号的低电平控制器，其中高电平控制器和低电平控制器中的一个被配置为产生初始脉冲信号在初期阶段。驱动电路还包括与M移位寄存器级联的起始单元，其中起始单元被配置为向移位寄存器提供启动信号。

87. 发明申请

US20170061912A1 LIQUID CRYSTAL DISPLAY 审中-公开
标题翻译：液晶显示器
公开(公告)号：US20170061912A1
公开(公告)日：2017-03-02
申请号：US14887866
申请日：2015-10-20
申请人： SHARP KABUSHIKI KAISHA
发明人： Masae KITAYAMA , Fumikazu SHIMOSHIKIRYOH , Kentaroh IRIE , Toshihide TSUBATA , Naoshi YAMADA , Hidetoshi NAKAGAWA
IPC分类号： G09G3/36 , G11C19/00 , G09G3/20
CPC分类号： G09G3/3677 , G02F1/133707 , G02F1/134336 , G02F1/1362 , G02F1/1368 , G02F2001/134345 , G02F2201/122 , G02F2201/123 , G09G3/2077 , G09G3/3614 , G09G3/3655 , G09G3/3666 , G09G3/3688 , G09G2300/0413 , G09G2300/0426 , G09G2300/0443 , G09G2300/0447 , G09G2300/0876 , G09G2310/0224 , G09G2310/0286 , G09G2310/06 , G09G2310/08 , G09G2320/0233 , G11C19/00
摘要： In one embodiment of the present invention, each pixel includes first and second subpixels. CS bus lines connected to the respective storage capacitors of the first and second subpixels are electrically independent of each other. A CS voltage has a waveform that inverts its polarity at least once a frame, which includes a first subframe for sequentially scanning a series of odd rows and a second SF for sequentially scanning even rows that have been skipped during the first SF. A source signal voltage varies so as to have two frames or subframes with mutually opposite polarities. A CS voltage has a waveform that has quite opposite consequences on the effective voltage of a subpixel of a pixel connected to the jth scan line to be selected during the first subframe and on that of another subpixel of a pixel connected to the (j+1)th scan line to be selected during the second subframe. In this manner, the deterioration in display quality, which would be caused if either a source line inversion drive or a block inversion drive is applied to a multi-pixel technology, can be minimized.
摘要翻译：在本发明的一个实施例中，每个像素包括第一和第二子像素。连接到第一和第二子像素的各个存储电容器的CS总线彼此电独立。 CS电压具有至少一帧反转其极性的波形，其包括用于顺序扫描一系列奇数行的第一子帧和用于顺序扫描在第一SF期间被跳过的偶数行的第二SF。源极信号电压发生变化，从而具有相互极性相反的两个帧或子帧。 CS电压具有与第一子帧期间要选择的第j扫描线连接的像素的子像素的有效电压和连接到第（j + 1）像素的像素的另一子像素的有效电压具有相反的结果的波形）扫描线在第二子帧期间被选择。以这种方式，如果将源极线反转驱动或块反转驱动应用于多像素技术，则会导致显示质量的劣化。

88. 发明申请

US20170036443A1 DRIVING CIRCUIT FOR DRIVING A CAPACITIVE LOAD 审中-公开
标题翻译：用于驱动电容负载的驱动电路
公开(公告)号：US20170036443A1
公开(公告)日：2017-02-09
申请号：US15299669
申请日：2016-10-21
申请人： Seiko Epson Corporation
发明人： Shuji OTSUKA , Tadashi KIYUNA , Toshifumi ASANUMA
IPC分类号： B41J2/045 , H03K19/018 , G11C19/00
CPC分类号： B41J2/04541 , B41J2/04573 , B41J2/04581 , B41J2/04586 , B41J2/04588 , G11C19/00 , H03K19/01806
摘要： A driving circuit for driving a capacitive load includes: an original drive signal generator that generates a plurality of original drive signals which includes a first original drive signal and a second original drive signal; a selection section that is capable of selecting one original drive signal from the plurality of original drive signals which includes the first original drive signal and the second original drive signal; a driver that generates a drive signal of voltages in accordance with the one original drive signal.
摘要翻译：用于驱动电容性负载的驱动电路包括：原始驱动信号发生器，其产生包括第一原始驱动信号和第二原始驱动信号的多个原始驱动信号; 选择部分，其能够从包括第一原始驱动信号和第二原始驱动信号的多个原始驱动信号中选择一个原始驱动信号; 根据一个原始驱动信号产生电压的驱动信号的驱动器。

89. 发明授权

US09524686B2 Shift register unit, gate electrode drive circuit and display apparatus 有权
标题翻译：移位寄存器单元，栅电极驱动电路和显示装置
公开(公告)号：US09524686B2
公开(公告)日：2016-12-20
申请号：US14436932
申请日：2014-07-30
申请人： BOE Technology Group Co., Ltd.
发明人： Yuanbo Zhang , Jiayang Zhao , Seung Woo Han , Xing Yao , Haifeng Jin
IPC分类号： G09G3/36 , G11C19/00 , G06F3/041 , G11C19/28
CPC分类号： G09G3/3648 , G06F3/0416 , G09G3/36 , G09G3/3674 , G09G3/3696 , G09G2300/0426 , G09G2310/0286 , G09G2310/08 , G11C19/00 , G11C19/28 , G11C19/287
摘要： The present disclosure provides a shift register unit, a gate electrode drive circuit and a display apparatus, which relates to a technical field of display. The shift register unit includes an input reset module, a pull up module, a control module and a pull down module. By inputting a high level into the second signal input end of the input reset module in the touch scan to maintain the level at the pull up control node, the electrical leak effects at the pull up control node may be avoided efficiently. In this way, the defects of insufficient charging rate of the row pixels may be avoided and the dark lines or bad bright lines may be suppressed.
摘要翻译：本公开提供了一种与显示技术领域有关的移位寄存器单元，栅电极驱动电路和显示装置。移位寄存器单元包括输入复位模块，上拉模块，控制模块和下拉模块。通过在触摸扫描中将高电平输入到输入复位模块的第二信号输入端以维持上拉控制节点处的电平，可以有效地避免上拉控制节点处的电泄漏效应。以这种方式，可以避免行像素充电速率不足的缺陷，并且可以抑制暗线或不良亮线。

90. 发明申请

US20160358536A1 DATA ACQUISITION MODULE AND METHOD, DATA PROCESSING UNIT, DRIVER AND DISPLAY DEVICE 有权
标题翻译：数据采集模块和方法，数据处理单元，驱动器和显示设备
公开(公告)号：US20160358536A1
公开(公告)日：2016-12-08
申请号：US14894923
申请日：2015-05-19
申请人： BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. , BOE TECHNOLOGY GROUP CO., LTD.
发明人： Mubing LI , Pengcheng LU , Xue DONG , Renwei GUO
IPC分类号： G09G3/20 , G11C19/00
CPC分类号： G09G3/2096 , G09G3/20 , G09G3/2003 , G09G5/04 , G09G2300/0452 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G09G2340/0457 , G11C19/00 , G11C19/287
摘要： The present invention provides a data acquiring module, comprising: a data input and output terminal, through which date enter into the data acquiring module, and which can output data independently; a shift register groups, each of which comprises (b−1) serially connected shift registers, and an output terminal of each shift register being able to output data independently, wherein a and b are integers greater than 1; and (a−1) serially connected first-in first-out memories connected to (a−1) shift register groups respectively, and the output terminal of each first-in first-out memory being able to output data independently, an input terminal of the last shift register in the shift register group without a corresponding first-in first-out memory in the a shift register groups, and the input terminal of the last first-in first-out memory of the serially connected first-in first-out memories being connected to the data input and output terminal. The present invention also provides a data processing unit, a driver and a display device.
摘要翻译：本发明提供了一种数据获取模块，包括：数据输入和输出终端，通过该数据输入和输出终端进入数据获取模块，并且可独立地输出数据; 移位寄存器组，每个移位寄存器组包括（b-1）串行移位寄存器，并且每个移位寄存器的输出端能够独立地输出数据，其中a和b是大于1的整数; 和（a-1）串联连接的先（a-1）移位寄存器组的先进先出存储器，并且每个先进先出存储器的输出端能够独立地输出数据，输入端在移位寄存器组中没有相应的先进先出存储器的移位寄存器组中的最后一个移位寄存器，以及串行连接的先进先出存储器的输入端，输出存储器连接到数据输入和输出端子。本发明还提供一种数据处理单元，驱动器和显示装置。

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