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1. 发明申请

US20190181868A1 CLOCK AND DATA RECOVERY (CDR) CIRCUIT 审中-公开
公开(公告)号：US20190181868A1
公开(公告)日：2019-06-13
申请号：US15901212
申请日：2018-02-21
申请人： Synopsys, Inc.
发明人： Biman Chattopadhyay , Jairaj Naik K R
IPC分类号： H03L7/08 , H03L7/089 , H04L7/00
CPC分类号： H03L7/0802 , H03L7/0807 , H03L7/0895 , H04L7/0008
摘要： A clock and data recovery (CDR) circuit for data sampling includes a sampler, a phase detector, a proportional-integral (PI) controller, and an oscillator. The sampler receives a data signal and a clock signal, and generates first, second, and third sampled signals. The phase detector receives the first, second, and third sampled signals, and generates first and second early-late vote (ELV) signals. The charge pump steers a current signal into or out of one of summing nodes based on the first and second ELV signals. The integrator circuit receives the current signal from one of the summing nodes, and generates a first control signal. The proportional circuit receives the first and second ELV signals, and generates a second control signal. The oscillator receives the first and second control signals from the integrator and proportional circuits, respectively, and generates a clock signal for sampling the data.

2. 发明申请

US20180358087A1 DISTRIBUTED SINKING CIRCUIT CONTROL FOR MEMORY DEVICE 审中-公开
公开(公告)号：US20180358087A1
公开(公告)日：2018-12-13
申请号：US15874156
申请日：2018-01-18
申请人： SanDisk Technologies LLC
发明人： Albert CHANG , Khin HTOO , Matt CHEN
IPC分类号： G11C11/56 , H03L7/089 , G11C16/10 , G11C17/12 , G11C16/04
CPC分类号： G11C11/5628 , G11C5/063 , G11C5/14 , G11C7/12 , G11C13/0023 , G11C13/0038 , G11C16/0416 , G11C16/08 , G11C16/102 , G11C16/30 , G11C17/12 , H03L7/0895
摘要： Disclosed is a device including a sinking circuit to sink current from an output node and a driver circuit coupled to the sinking circuit. The driver circuit includes complimentary differential pairs to receive a voltage at the output node and generate a control signal according to the received voltage. The sinking circuit is configured to change the current from the output node according to the control signal.

3. 发明授权

US09859902B2 Systems and method involving fast-acquisition lock features associated with phase locked loop circuitry 有权
公开(公告)号：US09859902B2
公开(公告)日：2018-01-02
申请号：US15442375
申请日：2017-02-24
申请人： GSI Technology, Inc.
发明人： Chao-Hung Chang
IPC分类号： H03L7/08 , H03L7/089 , H03L7/087
CPC分类号： H03L7/0891 , H03L7/0807 , H03L7/087 , H03L7/089 , H03L7/0895 , H03L7/113
摘要： Systems and methods are disclosed relating to fields of clock/data acquisition or handling, such as clock/data locking and the like. In one exemplary implementation, phase lock loop (PLL) circuitry may comprise voltage controlled oscillator (VCO) circuitry, phase frequency detector, converting circuitry, and frequency detector (FD) circuitry that outputs a frequency difference signal proportional to frequency difference between frequencies of a feedback clock signal and a reference clock signal.

4. 发明授权

US09742415B1 Apparatus for linearizing a differential charge pump 有权
公开(公告)号：US09742415B1
公开(公告)日：2017-08-22
申请号：US15281736
申请日：2016-09-30
申请人： Quantenna Communications, Inc.
发明人： Shirin Chegeni , Koushik Krishnan
IPC分类号： H02M3/07 , H03L7/089 , H03L7/099
CPC分类号： H03L7/0891 , H03L7/0895 , H03L7/0896 , H03L7/099 , H03L7/18 , H03L7/1976
摘要： A charge pump and a differential phase locked loop incorporating the charge pump. The charge pump includes a differential charge pump and an auxiliary charge pump. The differential charge pump has differential inputs and primary and mirror outputs. The differential charge pump is responsive to a down signal at the differential inputs to provide a negative current at the primary output and a positive current at the mirror output, and further responsive to an up signal at the differential inputs to provide a positive current at the primary output and a negative current at the mirror output. The auxiliary charge pump has differential inputs and an auxiliary output coupled to the mirror output of the differential charge pump. The differential charge pump is responsive to the down signal at the differential inputs to provide a negative current at the auxiliary output, and responsive to the up signal at the differential inputs to provide a positive current at the auxiliary output.

5. 发明授权

US09680483B2 Current mirror circuit and charge pump circuit 有权
公开(公告)号：US09680483B2
公开(公告)日：2017-06-13
申请号：US14573855
申请日：2014-12-17
申请人： FUJITSU LIMITED
发明人： Yukito Tsunoda
IPC分类号： G05F3/26 , H03L7/089 , H03K5/24 , H02M3/07
CPC分类号： H03L7/0895 , G05F3/26 , G05F3/262 , H02M3/07 , H03K5/24 , H03K5/2481 , H03L7/08
摘要： A current mirror circuit includes: a reference current circuit including a reference transistor and a constant current source coupled between a high potential source and a low potential source; a first proportional current circuit, including a first transistor that forms a first current mirror circuit with the reference transistor, to generate a first current having a first ratio to a reference current of the reference current circuit; a second proportional current circuit, including a second transistor that forms a second current mirror circuit with the reference transistor, to generate a second current having a second ratio to the reference current; a comparison circuit to output a difference between a drain voltage of the first transistor and a drain voltage of the second transistor; and a current adjustment transistor coupled to a drain of the second transistor and including a gate to which an output of the comparison circuit is applied.

6. 发明授权

US09496880B1 Fully differential charge pump with switched-capacitor common-mode feedback 有权
标题翻译：全差分电荷泵，带开关电容共模反馈
公开(公告)号：US09496880B1
公开(公告)日：2016-11-15
申请号：US14826888
申请日：2015-08-14
申请人： QUALCOMM Incorporated
发明人： Wenjing Yin , Jeffrey Mark Hinrichs
IPC分类号： H03L7/06 , H03L7/089 , H02M3/07
CPC分类号： H03L7/0891 , H02M3/07 , H03L7/087 , H03L7/0895 , H03L7/0896
摘要： Certain aspects of the present disclosure provide methods and apparatus for implementing a fully differential charge pump circuit that eliminates a source of noise and power consumption by using a low-noise switched-capacitor common-mode feedback (CMFB) circuit, rather than a continuous-time amplifier-based CMFB circuit. The fully differential charge pump circuit presented in this disclosure includes the switched-capacitor CMFB (SC-CMFB) unit connected to differential output nodes of the charge pump and provides a feedback signal to the charge pump to control a common-mode voltage of the differential signals based on a reference common-mode voltage. In certain aspects, a replica phase-frequency detector (PFD), a frequency divider, and a non-overlapping clock generator provides control signals for the SC-CMFB circuit.
摘要翻译：本公开的某些方面提供了用于实现完全差分电荷泵电路的方法和装置，其通过使用低噪声开关电容器共模反馈（CMFB）电路而不是连续的电路来消除噪声源和功率消耗源，基于时间放大器的CMFB电路。在本公开中呈现的全差分电荷泵电路包括连接到电荷泵的差分输出节点的开关电容器CMFB（SC-CMFB）单元，并向电荷泵提供反馈信号以控制差分的共模电压基于参考共模电压的信号。在某些方面，复制相位频率检测器（PFD），分频器和非重叠时钟发生器为SC-CMFB电路提供控制信号。

7. 发明申请

US20160308538A1 PHASE-LOCKED LOOP WITH LOWER POWER CHARGE PUMP 有权
标题翻译：具有较低功率充电泵的相位锁定环
公开(公告)号：US20160308538A1
公开(公告)日：2016-10-20
申请号：US15194533
申请日：2016-06-27
申请人： INTEL CORPORATION
发明人： Gennady GOLTMAN , Yongping FAN , Kuan-Yueh SHEN
IPC分类号： H03L7/08 , H03L7/093 , H03L7/089
CPC分类号： H03L7/0802 , H03L7/085 , H03L7/089 , H03L7/0895 , H03L7/093
摘要： Described is a phase-locked loop with lower power charge pump. The phase-locked loop comprises: a phase frequency detector to compare a reference clock and a feedback clock and generate a pulse based on the comparison, a charge pump to provide a charge signal corresponding to the pulse, a bias generator to provide biasing for the charge pump, wherein the bias generator is operable to receive a bias enable signal from the phase frequency detector and the bias generator is disabled when the bias enable signal is not asserted, a loop filter coupled to the output of the charge pump to provide a control signal responsive to the charge signal, and a voltage-controlled oscillator (VCO), wherein the oscillating frequency of the VCO is controlled by the control signal.
摘要翻译：描述的是具有较低功率电荷泵的锁相环。锁相环包括：相位频率检测器，用于比较参考时钟和反馈时钟，并基于比较产生脉冲，电荷泵以提供对应于脉冲的电荷信号;偏置发生器，用于为电荷泵，其中所述偏置发生器可操作以从所述相位频率检测器接收偏置使能信号，并且当所述偏置使能信号未被置位时，所述偏置发生器被禁用;环路滤波器耦合到所述电荷泵的输出以提供控制响应于充电信号的信号，以及压控振荡器（VCO），其中VCO的振荡频率由控制信号控制。

8. 再颁专利

USRE46107E1 Integrated circuits including a charge pump circuit and operating methods thereof 有权
标题翻译：包括电荷泵电路的集成电路及其操作方法
公开(公告)号：USRE46107E1
公开(公告)日：2016-08-16
申请号：US14284181
申请日：2014-05-21
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Steven Swei , Chih-Chang Lin , Tien-Chun Yang , Chan-Hong Chern , Ming-Chieh Huang
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F1/10 , G05F3/02 , H03L7/0895 , H03L7/0896 , H03L7/0898
摘要： An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.
摘要翻译：集成电路包括第一电流源。第二电流源经由导线与第一电流源电耦合。开关电路耦合在第一电流源和第二电流源之间。第一电路耦合在第一节点和第二节点之间。第一节点设置在第一电流源和开关电路之间。第二节点与第一电流源耦合。第一电路被配置为基本上均衡第一节点和第二节点上的电压。第二电路耦合在第三节点和第四节点之间。第三节点设置在第二电流源和开关电路之间。第四节点被布置成与第二电流源耦合。第二电路被配置为基本上均衡第三节点和第四节点上的电压。

9. 发明授权

US09214946B2 Phase locked loop circuit 有权
标题翻译：锁相环电路
公开(公告)号：US09214946B2
公开(公告)日：2015-12-15
申请号：US14108834
申请日：2013-12-17
申请人： Samsung Electronics Co., Ltd.
发明人： Nan Xing , Jaejin Park , Jenlung Liu , Tae-Kwang Jang
IPC分类号： H03L7/06 , H03L7/093 , H03L7/089
CPC分类号： H03L7/093 , H03L7/0895
摘要： A phase locked loop circuit is provided which includes a bang-bang phase frequency detector configured to receive a reference signal and a feedback signal, detect a phase difference between the reference signal and the feedback signal, output a detection signal on the based on a result of the detection; an analog-digital mixed filter configured to receive the detection signal and output a control signal on the basis of the received detection signal; a voltage controlled oscillator configured to output an output signal in response to the control signal; and a divider configured to divide the output signal by n to output as the feedback signal. The detection signal is a digital signal, and the control signal is an analog signal.
摘要翻译：提供了一种锁相环电路，其包括一个轰击相位频率检测器，配置为接收参考信号和反馈信号，检测参考信号和反馈信号之间的相位差，基于结果输出检测信号的检测; 模拟数字混合滤波器，被配置为接收检测信号并根据接收到的检测信号输出控制信号; 被配置为响应于所述控制信号输出输出信号的压控振荡器; 以及分频器，被配置为将输出信号除以n作为反馈信号输出。检测信号是数字信号，控制信号是模拟信号。

10. 发明授权

US09065457B2 Circuits and methods for eliminating reference spurs in fractional-N frequency synthesis 有权
$Circuits and methods for eliminating reference spurs in fractional-N frequency synthesis$
标题翻译：用于消除分数N频率合成中的参考杂散的电路和方法
公开(公告)号：US09065457B2
公开(公告)日：2015-06-23
申请号：US13870742
申请日：2013-04-25
申请人： Skyworks Solutions, Inc.
发明人： Ardeshir Namdar-Mehdiabadi , Darren Roger Frenette , John William Mitchell Rogers
IPC分类号： H03D3/24 , H03L7/197 , H04L7/00 , H03L7/089
CPC分类号： H03L7/1974 , H03L7/087 , H03L7/0891 , H03L7/0895 , H03L7/0898 , H03L7/093 , H03L7/099 , H03L7/197 , H03L7/1976 , H03L7/1978 , H04L7/0016 , H04L7/0045 , H04W56/0035 , H04W88/02
摘要： Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL.
摘要翻译：公开了用于减少或消除频率合成器中的参考杂散的电路和方法。在一些实现中，诸如频率合成器的Frac-N PLL的锁相环（PLL）可以包括被配置为接收参考信号和反馈信号的相位频率检测器（PFD）。 PFD可以被配置为产生表示参考信号和反馈信号之间的相位差的第一信号。 PLL还可以包括被配置为基于第一信号产生补偿信号的补偿电路。 PLL还可以包括被配置为基于补偿信号产生输出信号的压控振荡器（VCO）。补偿信号可以包括用于基本上消除与PLL相关联的一个或多个参考杂波的至少一个特征。

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