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81. 发明授权

US4608678A Semiconductor memory device for serial scan applications 失效
标题翻译：用于串行扫描应用的半导体存储器件
公开(公告)号：US4608678A
公开(公告)日：1986-08-26
申请号：US564969
申请日：1983-12-23
申请人： N. Bruce Threewitt
发明人： N. Bruce Threewitt
IPC分类号： G06F3/153 , G06F12/00 , G09G1/02 , G09G1/16 , G09G5/00 , G09G5/14 , G09G5/34 , G09G5/39 , G09G5/395 , G11C8/04 , G11C13/00
CPC分类号： G09G5/395 , G11C8/04 , G09G5/14 , G09G5/34
摘要： An improved semiconductor memory device for serial scan applications is presented. The semiconductor memory device as presented includes a main memory means combined with an on-board means for implementing a shift register function. The shift register function of the present invention is implemented by utilizing a secondary memory means in conjunction with parallel loadable, multiple-bit address counters.
摘要翻译：提出了一种用于串行扫描应用的改进的半导体存储器件。所呈现的半导体存储器件包括与用于实现移位寄存器功能的板上装置组合的主存储器装置。本发明的移位寄存器功能通过利用辅助存储器结合并行可加载的多位地址计数器来实现。

82. 发明授权

US4460958A Window-scanned memory 失效
标题翻译：窗口扫描存储器
公开(公告)号：US4460958A
公开(公告)日：1984-07-17
申请号：US298268
申请日：1981-08-31
申请人： Lauren A. Christopher , Glenn A. Reitmeier , Terrence R. Smith , Christopher H. Strolle
发明人： Lauren A. Christopher , Glenn A. Reitmeier , Terrence R. Smith , Christopher H. Strolle
IPC分类号： G06F1/02 , G06F1/03 , G06F7/548 , G06F12/02 , G06F17/17 , G06G7/26 , G09G5/39 , G11C7/00 , G11C8/04 , G11C8/12 , G11C8/16 , H03H17/02 , H03H17/06 , H04N9/78 , G06F13/06
CPC分类号： H04N9/78 , G06F1/0307 , G06F12/0207 , G06F17/175 , G09G5/39 , G11C7/00 , G11C8/04 , G11C8/12 , G11C8/16 , H03H17/0202 , H03H17/06 , G06F2101/04 , G06F2101/08 , G06F2101/10 , G09G2310/0224 , G09G2360/123
摘要： The storage locations of a memory system map a field of sample points. Apparatus affording parallel access to a plurality of storage locations describing an array of the sample points in an access window, which window can be shifted to any selected region of field of sample points responsive to orthogonal address coordinates of one of the sample points in the array, is described.
摘要翻译：存储系统的存储位置映射采样点的场。提供并行访问多个存储位置的描述在访问窗口中的采样点阵列的多个存储位置，该窗口可以响应于阵列中的一个采样点的正交地址坐标而移动到采样点的任何选定的场域，被描述。

83. 发明授权

US4432055A Sequential word aligned addressing apparatus 失效
标题翻译：顺序字对齐寻址装置
公开(公告)号：US4432055A
公开(公告)日：1984-02-14
申请号：US306839
申请日：1981-09-29
申请人： Edward R. Salas , Chester M. Nibby, Jr. , Robert B. Johnson
发明人： Edward R. Salas , Chester M. Nibby, Jr. , Robert B. Johnson
IPC分类号： G06F12/06 , G06F12/04 , G06F13/00 , G11C8/04 , G11C11/4063
CPC分类号： G06F12/04 , G11C11/4063 , G11C8/04
摘要： A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem further includes an adder circuit, a pair of tristate operated address register circuits and timing circuits. The address circuits include a pair of tristate operated address registers which couple to the bus and to the set of address lines to each memory unit. In response to a memory request, the registers store row and column address portions of a chip address of the memory request. A multibit adder circuit which couples to the bus is connected to increment by one the low order column address portion when the least significant address bit of the memory request indicates a subboundary address condition thereby enabling access to a pair of sequential word locations. Whenever a memory request specifies an address which cannot access a double word, boundary circuits upon detecting the condition cause the timing circuits to generate only timing signals necessary for accessing the first word location.
摘要翻译：耦合到多字总线以用于处理从其接收的存储器请求的存储器子系统包括至少一对独立可寻址的动态存储器模块单元。每个存储器单元包括多行随机存取存储器（RAM）芯片。子系统还包括加法器电路，一对三态操作地址寄存器电路和定时电路。地址电路包括一对三态操作的地址寄存器，其耦合到总线和到每个存储器单元的一组地址线。响应于存储器请求，寄存器存储存储器请求的芯片地址的行和列地址部分。当存储器请求的最低有效地址位指示子边界地址条件从而使得能够访问一对顺序字位置时，耦合到总线的多位加法器电路被连接以递增低位列地址部分的一个。每当存储器请求指定不能访问双字的地址时，边界电路打开检测状态使得定时电路只产生访问第一字位置所必需的定时信号。

84. 发明授权

US4354256A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4354256A
公开(公告)日：1982-10-12
申请号：US145346
申请日：1980-04-30
申请人： Kiyoshi Miyasaka
发明人： Kiyoshi Miyasaka
IPC分类号： G11C11/41 , G06F12/04 , G06F12/06 , G11C7/10 , G11C8/04 , G11C11/409 , G11C11/4096 , G11C11/417 , G11C11/419 , G11C11/40
CPC分类号： G11C7/1006 , G06F12/04 , G11C11/409 , G11C11/4096 , G11C11/419 , G11C8/04
摘要： A semiconductor memory device, comprising N memory cell arrays each of which includes a plurality of memory cells, is arranged to enable the use of said semiconductor memory device in the form of both one-bit-per-word N-bits-per-word. Two separate sets of output gates are provided, together with an additional input line for selecting between the two sets of gates. One set of gates is connected to provide one-bit output, and the other set of gates is connected to provide N-bit output.
摘要翻译：一种包括N个存储单元阵列的半导体存储器件，每个存储单元阵列包括多个存储器单元，被配置为使得能够以一位一字节N位单位字的形式使用所述半导体存储器件。提供两组独立的输出门，以及用于在两组门之间进行选择的附加输入线。一组门连接以提供一位输出，另一组门连接以提供N位输出。

85. 发明授权

US4281401A Semiconductor read/write memory array having high speed serial shift register access 失效
标题翻译：具有高速串行移位寄存器访问的半导体读/写存储器阵列
公开(公告)号：US4281401A
公开(公告)日：1981-07-28
申请号：US96957
申请日：1979-11-23
申请人： Donald J. Redwine , Lionel S. White, Jr. , G. R. Mohan Rao
发明人： Donald J. Redwine , Lionel S. White, Jr. , G. R. Mohan Rao
IPC分类号： G11C8/04 , G11C11/4096 , G11C11/40
CPC分类号： G11C8/04 , G11C11/4096
摘要： A semiconductor memory device of the MOS/LSI type using an array of dynamic one-transistor cells has a high speed serial input/output system. A serial shift register having a number of stages equal to the number of columns in the memory cell array is split into two half registers connected to opposite sides of the columns by transfer gates. The bits in the register may be loaded into the columns of the array and thus to an addressed row of cells, or data in one entire addressed row of cells may be loaded into the shift register stages via the columns and transfer gates. For a write operation, data from external is loaded serially into the shift register, alternating bit by bit between the two half registers. For a read operation, data is serially shifted out of the register to external, again alternating between the half registers. The data register can be advanced at twice the clock frequency. The cell array can be addressed for refresh during the time that data is being shifted into or out of the serial register.
摘要翻译：使用动态单晶体管单元阵列的MOS / LSI型半导体存储器件具有高速串行输入/输出系统。具有等于存储单元阵列中的列数的级数的串行移位寄存器被分离成通过传输门连接到列的相对侧的两个半寄存器。寄存器中的位可以被加载到阵列的列中，并且因此被加载到寻址的单元行，或者一个整个寻址的单元行的数据可以经由列和传送门被加载到移位寄存器级。对于写操作，来自外部的数据被串行地加载到移位寄存器中，在两个半寄存器之间逐位交替。对于读操作，数据从寄存器中串行移出到外部，再次在半寄存器之间交替。数据寄存器可以以两倍的时钟频率进行。在数据被移入或移出串行寄存器的时间期间，单元阵列可被寻址以进行刷新。

86. 发明授权

US4153951A Event marker having extremely small bit storage requirements 失效
标题翻译：事件标记具有非常小的位存储要求
公开(公告)号：US4153951A
公开(公告)日：1979-05-08
申请号：US726392
申请日：1976-09-24
申请人： George L. Slenkovich
发明人： George L. Slenkovich
IPC分类号： G01S1/68 , G06F12/06 , G11C8/04 , G11C19/00
CPC分类号： G11C8/04
摘要： A plurality of random access memories (RAMS) are each addressed by a binary sub-number, all sub-numbers making up a composite binary address number, the maximum count of which defines the total number of subintervals within a given pulse repetition interval. The data output terminals of each RAM are coupled to an associated input terminal of an AND gate so that the AND gate produces an event mark once during each pulse repetition interval upon the detection of a bit readout of each RAM simultaneously during the particular subinterval when the event occurs.
摘要翻译：多个随机存取存储器（RAMS）分别由二进制子号码，所有子编号构成复合二进制地址号码，其最大计数定义给定脉冲重复间隔内的子间隔的总数。每个RAM的数据输出端子耦合到与门的相关输入端，使得与门在每个脉冲重复间隔期间产生一次事件标记，当在特定子间隔期间同时检测每个RAM的位读出时事件发生。

87. 发明授权

US4150430A Information selection device 失效
标题翻译：信息选择装置
公开(公告)号：US4150430A
公开(公告)日：1979-04-17
申请号：US811848
申请日：1977-06-30
申请人： Valery F. Gusev , Gennady N. Ivanov , Vladimir Y. Kontarev , Vyacheslav Y. Kremlev , Mansur Z. Shagivaleev , Jury I. Schetinin , Azat U. Yarmukhametov , Genrikh I. Krengel
发明人： Valery F. Gusev , Gennady N. Ivanov , Vladimir Y. Kontarev , Vyacheslav Y. Kremlev , Mansur Z. Shagivaleev , Jury I. Schetinin , Azat U. Yarmukhametov , Genrikh I. Krengel
IPC分类号： G06F9/00 , G06F9/22 , G06F9/26 , G06F9/42 , G06F12/02 , G11C7/00 , G11C8/04 , G06F7/02
CPC分类号： G06F9/264
摘要： The proposed information selection device includes an initial address register and a memory address forming unit. The forming unit is electrically connected to two coincidence circuits, a functional return address jump register and a control information decoder. The control information decoder is connected to a memory unit for storing control information. A constant register connected to the functional return address jump register. A control information register is connected to the control information decoder. The control information decoder is connected to each of the coincidence circuits. An analysis signal register is connected to an analysis signal forming decoder. A comparison code register and a comparison mask register are also included. To both coincidence circuits there is connected a comparison unit for comparing information, which is being analyzed, with a respective code. The comparison unit is electrically coupled to the analysis signal forming decoder, the initial address register, the comparison code register, the comparison mask register, two counters, two data buses and a state of the device analysis buffer register connected to the control information decoder. The device of the present invention makes it possible to select any information code digits required for the ayalysis and analyze them by comparing them with the reference code value.
摘要翻译：所提出的信息选择装置包括初始地址寄存器和存储器地址形成单元。形成单元电连接到两个重合电路，功能返回地址跳转寄存器和控制信息解码器。控制信息解码器连接到用于存储控制信息的存储单元。连接到功能返回地址跳转寄存器的常量寄存器。控制信息寄存器连接到控制信息解码器。控制信息解码器连接到每个符合电路。分析信号寄存器连接到分析信号形成解码器。还包括比较码寄存器和比较掩码寄存器。对于两个符合电路，连接有比较单元，用于将正在分析的信息与相应的代码进行比较。比较单元电耦合到分析信号形成解码器，初始地址寄存器，比较代码寄存器，比较掩码寄存器，两个计数器，两个数据总线以及连接到控制信息解码器的器件分析缓冲寄存器的状态。本发明的装置使得可以选择分析所需的任何信息代码数字，并通过将它们与参考代码值进行比较来分析它们。

88. 发明授权

US4099259A Data stores and data storage system 失效
标题翻译：数据存储和数据存储系统
公开(公告)号：US4099259A
公开(公告)日：1978-07-04
申请号：US731248
申请日：1976-10-12
申请人： Robert Parsons , Howard Cook
发明人： Robert Parsons , Howard Cook
IPC分类号： H04N7/025 , G09G5/22 , G11C8/04 , H04L29/00 , H04N7/03 , H04N7/035 , H04N7/088 , G06F13/06
CPC分类号： H04N7/0882 , G09G5/222
摘要： In a Teletext transmission system, data is transmitted in digital form during lines in the field blanking period of a composite video signal of a television transmission. On reception, the information is decoded and utilized to provide a display comprising a page having a predetermined number of rows of information in alphanumeric or graphics form. The data is received in blocks comprising information digits and each block has an associated group of address digits so that each block can be directed to an appropriate storage location in a first store, regardless of the order in which the data blocks are transmitted. The contents of the first store can then be transferred in address order into a larger capacity serial store ready for use in generating the display. Thus it is possible for a number of pages of information data to be correctly assembled in serial row order, ready for display generation, in a manner accommodating non-transmitted blank rows.
摘要翻译：在图文电视传输系统中，数据在电视传输的复合视频信号的场消隐期间的行中以数字形式发送。在接收时，信息被解码并用于提供包括具有字母数字或图形形式的具有预定数量的信息行的页面的显示。在包括信息数字的块中接收数据，并且每个块具有相关联的地址数字组，使得每个块可以被引导到第一存储中的适当的存储位置，而不管发送数据块的顺序。然后可以将第一个商店的内容以地址顺序传送到准备好用于生成显示器的更大容量的串行存储器中。因此，可以以容纳未发送的空白行的方式，以串行顺序正确地组合多页信息数据，准备好进行显示生成。

89. 发明授权

US4069970A Data access circuit for a memory array 失效
标题翻译：存储器阵列的数据访问电路
公开(公告)号：US4069970A
公开(公告)日：1978-01-24
申请号：US699423
申请日：1976-06-24
申请人： Clair Alan Buzzard , Richard Cyril Gifford , Frank William Lescinsky , Robert Michael Zachok
发明人： Clair Alan Buzzard , Richard Cyril Gifford , Frank William Lescinsky , Robert Michael Zachok
IPC分类号： G06F3/16 , G06F5/00 , G06F11/00 , G06F11/10 , G06F12/02 , G11C7/00 , G11C8/00 , G11C8/04 , G11C27/00 , G11C29/00
CPC分类号： G11C8/00 , G06F11/0754 , G06F12/0207 , G06F3/16 , G06F5/00 , G11C7/00 , G11C8/04 , G06F11/1008
摘要： A memory array, having a plurality of intersecting rows and columns, stores digitized speech. Each row and column intersection consists of a binary storage cell for storing one bit of digitized speech. Incoming digitized speech is loaded into columns of the memory array in a plurality of repetitive loading sequences, each loading sequence including: reading out the bits stored in successive rows of binary storage cells, replacing in each successive row of bits, a predetermined one of the bits in the read out row with a successive one of the bits of the digitized speech and writing each read out row of bits including the replaced bit back into the row. Multibit binary grunts (digitized speech segments) stored in the array are read out therefrom by applying the bits of the grunts to time slots in frames on a time-division highway, each frame being of n bits duration and including one bit from each of n grunts stored in the array. A selected grunt is extracted from the highway by commencing a count of the bits on the highway with a first bit of the selected grunt and by extracting the first bit and every n.sup.th bit thereafter. Memory malfunction is indicated when the number of rows in the array containing parity errors exceeds a predetermined threshold number.
摘要翻译：具有多个相交行和列的存储器阵列存储数字化语音。每行和列交叉点由用于存储一位数字化语音的二进制存储单元组成。接收的数字化语音以多个重复加载序列被加载到存储器阵列的列中，每个加载序列包括：读出存储在二进制存储单元的连续行中的位，在每个连续的位行中替换预定的一个读出行中的位与数字化语音的连续的一个比特并且将每个读出的包括被替换的位的位的行写入行。存储在阵列中的多位二进制啁啾（数字化语音段）通过将啁啾的比特应用于时分高速公路上的帧中的时隙，每个帧的n位持续时间并且包括从n 咕噜存储在阵列中。通过使用所选咕噜的第一位开始高速公路上的比特的计数，并且之后提取第一比特和每第n个比特，从高速公路中提取所选择的咕噜声。当包含奇偶校验错误的阵列中的行数超过预定阈值时，会指示内存故障。

90. 发明授权

US4032904A Means for refreshing AC stable storage cells 失效
标题翻译：用于刷新AC稳定存储单元的方法
公开(公告)号：US4032904A
公开(公告)日：1977-06-28
申请号：US594382
申请日：1975-07-09
申请人： Kevin Lee Anderson , Luis Maria Arzubi
发明人： Kevin Lee Anderson , Luis Maria Arzubi
IPC分类号： G11C11/41 , G11C8/04 , G11C8/16 , G11C11/24 , G11C11/406 , G11C7/00
CPC分类号： G11C8/16 , G11C11/406 , G11C8/04
摘要： A refresh circuit for AC stable storage cells utilizing an asymmetric a stable power source for controlling an auxiliary shift register which in turn controls the refreshing shift register. The outputs of the refreshing shift register are coupled to the gate electrodes of gating devices coupled to the memory word line.

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