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81. 发明申请

US20130134391A1 Reducing Contact Resistance for Field-Effect Transistor Devices 有权
标题翻译：降低场效应晶体管器件的接触电阻
公开(公告)号：US20130134391A1
公开(公告)日：2013-05-30
申请号：US13306276
申请日：2011-11-29
申请人： Ali Afzali-Ardakani , Bhupesh Chandra , George S. Tulevski , Fengnian Xia
发明人： Ali Afzali-Ardakani , Bhupesh Chandra , George S. Tulevski , Fengnian Xia
IPC分类号： H01L29/772 , H01L21/28 , B82Y99/00
CPC分类号： B82Y10/00 , H01L29/0673 , H01L29/1606 , H01L29/66431 , H01L29/66742 , H01L29/7781 , H01L29/78618 , H01L29/78684 , H01L29/78696 , H01L51/0021 , H01L51/0048 , H01L51/0545 , H01L51/105
摘要： A method and an apparatus for doping a graphene and nanotube thin-film transistor field-effect transistor device to decrease contact resistance with a metal electrode. The method includes selectively applying a dopant to a metal contact region of a graphene and nanotube field-effect transistor device to decrease the contact resistance of the field-effect transistor device.
摘要翻译：一种用于掺杂石墨烯和纳米管薄膜晶体管场效应晶体管器件以降低与金属电极的接触电阻的方法和装置。该方法包括选择性地将掺杂剂施加到石墨烯和纳米管场效应晶体管器件的金属接触区域以降低场效应晶体管器件的接触电阻。

82. 发明申请

US20130126985A1 (110) SURFACE ORIENTATION FOR REDUCING FERMI-LEVEL-PINNING BETWEEN HIGH-K DIELECTRIC AND GROUP III-V COMPOUND SEMICONDUCTOR SUBSTRATE 有权
标题翻译：（110）用于降低高K电介质和III-V族化合物半导体衬底之间的电荷密度的表面定向
公开(公告)号：US20130126985A1
公开(公告)日：2013-05-23
申请号：US13299529
申请日：2011-11-18
申请人： Chao-Ching Cheng , Chih-Hsin Ko , Hsingjen Wann
发明人： Chao-Ching Cheng , Chih-Hsin Ko , Hsingjen Wann
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L29/785 , H01L21/28264 , H01L21/3081 , H01L29/045 , H01L29/0649 , H01L29/20 , H01L29/452 , H01L29/4916 , H01L29/517 , H01L29/66522
摘要： A device with improved device performance, and method of manufacturing the same, are disclosed. An exemplary device includes a group III-V compound semiconductor substrate that includes a surface having a (110) crystallographic orientation, and a gate stack disposed over the group III-V compound semiconductor substrate. The gate stack includes a high-k dielectric layer disposed on the surface having the (110) crystallographic orientation, and a gate electrode disposed over the high-k dielectric layer.
摘要翻译：公开了一种具有改进的器件性能的器件及其制造方法。示例性器件包括III-V族化合物半导体衬底，其包括具有（110）结晶取向的表面和设置在III-V族化合物半导体衬底上的栅叠层。栅极堆叠包括设置在具有（110）晶体取向的表面上的高k电介质层，以及设置在高k电介质层上的栅电极。

83. 发明申请

US20130119480A1 INTEGRATED CIRCUIT RESISTOR 有权
标题翻译：集成电路电阻
公开(公告)号：US20130119480A1
公开(公告)日：2013-05-16
申请号：US13294251
申请日：2011-11-11
申请人： King-Yuen Wong , Chia-Pin Lin , Chia-Yu Lu , Yi-Cheng Tsai , Da-Wen Lin , Kuo-Feng Yu
发明人： King-Yuen Wong , Chia-Pin Lin , Chia-Yu Lu , Yi-Cheng Tsai , Da-Wen Lin , Kuo-Feng Yu
IPC分类号： H01L29/772 , H01L21/02 , H01L29/02
CPC分类号： H01L28/20 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/26506 , H01L21/26513 , H01L21/823437 , H01L27/0629 , H01L29/66545 , H01L29/8605
摘要： A semiconductor device includes a substrate including an isolation region, and a resistor disposed over the isolation region, wherein the resistor includes an implant with an inverse box-like dopant profile that minimizes resistance variation from subsequent planarization variation. A contact is disposed over the resistor. A method of fabricating such a semiconductor device is also provided.
摘要翻译：半导体器件包括包括隔离区域的衬底和设置在隔离区域上的电阻器，其中电阻器包括具有反向盒状掺杂物分布的植入物，其使得电阻变化与随后的平坦化变化最小化。触点设置在电阻上。还提供了一种制造这种半导体器件的方法。

84. 发明申请

US20130119444A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130119444A1
公开(公告)日：2013-05-16
申请号：US13296908
申请日：2011-11-15
申请人： Chun-Fai CHENG , An-Shen CHANG , Hui-Min LIN , Tsz-Mei KWOK , Hsien-Ching LO
发明人： Chun-Fai CHENG , An-Shen CHANG , Hui-Min LIN , Tsz-Mei KWOK , Hsien-Ching LO
IPC分类号： H01L29/772 , H01L21/28 , H01L21/336
CPC分类号： H01L21/02639 , H01L21/02532 , H01L21/30604 , H01L21/30608 , H01L21/3065 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. The disclosed method comprises forming a wedge-shaped recess with an initial bottom surface in the substrate; transforming the wedge-shaped recess into an enlarged recess with a height greater than the height of the wedge-shaped recess; and epitaxially growing a strained material in the enlarged recess.
摘要翻译：公开了一种用于制造集成电路器件的集成电路器件和方法。所公开的方法包括在衬底中形成具有初始底表面的楔形凹部; 将楔形凹部转变成具有大于楔形凹部的高度的高度的扩大凹部; 并在扩大的凹部中外延生长应变材料。

85. 发明授权

US08441062B2 Nonvolatile memory devices having memory cell transistors therein with lower bandgap source/drain regions 有权
标题翻译：具有其中具有较低带隙源极/漏极区域的存储单元晶体管的非易失性存储器件
公开(公告)号：US08441062B2
公开(公告)日：2013-05-14
申请号：US12974542
申请日：2010-12-21
申请人： Byung-kyu Cho , Kwang-soo Seol , Sung-hoi Hur , Jung-dal Choi
发明人： Byung-kyu Cho , Kwang-soo Seol , Sung-hoi Hur , Jung-dal Choi
IPC分类号： H01L29/772
CPC分类号： H01L27/11521 , H01L27/11524
摘要： Nonvolatile memory devices include a plurality of nonvolatile memory cell transistors having respective channel regions within a semiconductor layer formed of a first semiconductor material and respective source/drain regions formed of a second semiconductor material, which has a smaller bandgap relative to the first semiconductor material. The source/drain regions can form non-rectifying junctions with the channel regions. The source/drain regions may include germanium (e.g., Ge or SiGe regions), the semiconductor layer may be a P-type silicon layer and the source/drain regions of the plurality of nonvolatile memory cell transistors may be P-type germanium or P-type silicon germanium.
摘要翻译：非易失性存储器件包括多个非易失性存储单元晶体管，其在由第一半导体材料形成的半导体层内的相应沟道区和由第二半导体材料形成的相应的源极/漏极区相互相对于第一半导体材料具有较小的带隙。源极/漏极区域可以与沟道区域形成非整流结。源极/漏极区域可以包括锗（例如Ge或SiGe区域），半导体层可以是P型硅层，并且多个非易失性存储单元晶体管的源极/漏极区域可以是P型锗或P 型硅锗。

86. 发明授权

US08436430B2 Diodes with embedded dummy gate electrodes 有权
标题翻译：具有嵌入式虚拟栅电极的二极管
公开(公告)号：US08436430B2
公开(公告)日：2013-05-07
申请号：US13082871
申请日：2011-04-08
申请人： Ming-Hsin Yu , Kvei-Feng Yen
发明人： Ming-Hsin Yu , Kvei-Feng Yen
IPC分类号： H01L29/772
CPC分类号： H01L29/861 , H01L27/0255
摘要： A circuit structure includes a first isolation region, and a first dummy gate electrode over and vertically overlapping the first isolation region. First pickup regions of a diode are formed on opposite sides of the first isolation region, wherein sidewalls of the first pickup regions contact opposite sidewalls of the first isolation region. Second pickup regions of the diode are formed on opposite sides of a combined region of the first pickup regions and the first isolation region, wherein the first and the second pickup regions are of opposite conductive types. A well region is under the first and the second pickup regions and the first isolation region, wherein the well region is of a same conductivity type as the second pickup regions.
摘要翻译：电路结构包括第一隔离区域和与第一隔离区域垂直重叠的第一伪栅极电极。二极管的第一拾取区域形成在第一隔离区域的相对侧上，其中第一拾取区域的侧壁接触第一隔离区域的相对侧壁。二极管的第二拾取区域形成在第一拾取区域和第一隔离区域的组合区域的相对侧上，其中第一和第二拾取区域具有相反的导电类型。阱区域位于第一和第二拾取区域和第一隔离区域之下，其中阱区域具有与第二拾取区域相同的导电类型。

87. 发明申请

US20130105914A1 STRUCTURE OF FIELD EFFECT TRANSISTOR WITH FIN STRUCTURE AND FABRICATING METHOD THEREOF 有权
标题翻译：具有结构的场效应晶体管结构及其制备方法
公开(公告)号：US20130105914A1
公开(公告)日：2013-05-02
申请号：US13281448
申请日：2011-10-26
申请人： Chien-Ting Lin
发明人： Chien-Ting Lin
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A method for fabricating a field effect transistor with fin structure includes the following steps. A substrate having an ion well with a first conductivity type is provided, wherein the ion well has a first doping concentration. At least a fin structure disposed on the substrate is formed. At least a first ion implantation is performed to form an anti-punch doped region with first conductivity type between the substrate and the channel layer, wherein the anti-punch doped region has a third doping concentration higher than the first doping concentration. At least a channel layer disposed along at least one surface of the fin structure is formed after the first ion implantation is performed. A gate covering part of the fin structure is formed. A source and a drain disposed in the fin structure beside the gate are formed, wherein the source and the drain have a second conductivity type.
摘要翻译：制造具有翅片结构的场效应晶体管的方法包括以下步骤。提供了具有第一导电类型的离子阱的衬底，其中离子阱具有第一掺杂浓度。至少形成设置在基板上的翅片结构。至少进行第一离子注入以在衬底和沟道层之间形成具有第一导电类型的抗冲击掺杂区域，其中抗冲击掺杂区域具有高于第一掺杂浓度的第三掺杂浓度。在执行第一离子注入之后，形成沿鳍片结构的至少一个表面设置的至少一个沟道层。形成覆盖翅片结构的一部分的栅极。形成在栅极旁边的翅片结构中设置的源极和漏极，其中源极和漏极具有第二导电类型。

88. 发明申请

US20130087832A1 Tucked Active Region Without Dummy Poly For Performance Boost and Variation Reduction 有权
标题翻译：没有虚拟聚合物的折叠活动区域用于性能提升和变化减少
公开(公告)号：US20130087832A1
公开(公告)日：2013-04-11
申请号：US13253375
申请日：2011-10-05
申请人： Xiaojun Yu , Brian J. Greene , Yue Liang
发明人： Xiaojun Yu , Brian J. Greene , Yue Liang
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/02112 , H01L21/02532 , H01L21/28123 , H01L21/76224 , H01L29/0649 , H01L29/165 , H01L29/66545 , H01L29/66553 , H01L29/66568 , H01L29/66636
摘要： In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided.
摘要翻译：在一个实施例中，提供了半导体器件，其包括半导体衬底，该半导体衬底包括有源区和位于有源区的周边的至少一个沟槽隔离区，以及存在于半导体衬底的有源区的一部分上的功能栅结构。嵌入式半导体区域存在于半导体衬底的有源区域中，在有源区域的存在功能栅极结构的部分的相对侧上。半导体衬底的有源区域的一部分将嵌入的半导体区域的最外边缘与至少一个隔离区域分开。还提供了形成上述装置的方法。

89. 发明申请

US20130083567A1 COMPOUND SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：化合物半导体器件及其制造方法
公开(公告)号：US20130083567A1
公开(公告)日：2013-04-04
申请号：US13551769
申请日：2012-07-18
申请人： Tadahiro Imada
发明人： Tadahiro Imada
IPC分类号： H01L29/772 , H02M5/458 , H01L21/20
CPC分类号： H01L29/41725 , H01L23/4824 , H01L23/49562 , H01L29/2003 , H01L29/42316 , H01L29/66462 , H01L29/7787 , H01L2224/05553 , H01L2224/05554 , H01L2224/0603 , H01L2224/32245 , H01L2224/45124 , H01L2224/48247 , H01L2224/48257 , H01L2224/48472 , H01L2224/4903 , H01L2224/73265 , H01L2924/12032 , H01L2924/181 , H01L2924/00 , H01L2924/00012
摘要： A compound semiconductor device includes an electron transit layer having a first polarity, a p-type cap layer which is formed above the electron transit layer and has a second polarity, and an n-type cap layer which is formed on the p-type cap layer and has the first polarity. The n-type cap layer includes portions having different thicknesses.
摘要翻译：化合物半导体器件包括具有第一极性的电子转移层，形成在电子转移层上方并具有第二极性的p型帽层，以及形成在p型帽上的n型帽层并具有第一极性。 n型盖层包括具有不同厚度的部分。

90. 发明申请

US20130082242A1 TRANSISTOR DEVICE WITH REDUCED GATE RESISTANCE 失效
公开(公告)号：US20130082242A1
公开(公告)日：2013-04-04
申请号：US13251637
申请日：2011-10-03
申请人： Shu-Jen Han , Alberto Valdes Garcia
发明人： Shu-Jen Han , Alberto Valdes Garcia
IPC分类号： H01L29/772 , H01L21/336 , H01L29/775 , B82Y99/00 , B82Y40/00
CPC分类号： H01L29/66742 , H01L29/42384 , H01L29/7781 , H01L29/78603 , H01L29/78636 , H01L29/78684
摘要： A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided.

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