专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明申请

US20110150110A1 Tone Count Selection 有权
标题翻译：音调选择
公开(公告)号：US20110150110A1
公开(公告)日：2011-06-23
申请号：US12655051
申请日：2009-12-22
申请人： Thomas J. Kenney , Eldad Perahia , Robert J. Stacey
发明人： Thomas J. Kenney , Eldad Perahia , Robert J. Stacey
IPC分类号： H04L27/28 , H04L27/02 , H04L27/10
CPC分类号： H04L27/2602 , H04L1/0003 , H04L1/0009 , H04L1/0041 , H04L1/0071 , H04L1/0075 , H04L5/0007 , H04L5/0048 , H04L27/2601 , H04L27/2626 , H04L27/2698 , Y02B70/30 , Y02D50/10
摘要： A tone selection module selects tones suitable for use in an orthogonal frequency division multiplexing (OFDM) data transmission device based on several constraints. These constraints include number of available tones, modulation type, and code rate. The OFDM device may use either wired or wireless transmission.
摘要翻译：音调选择模块基于若干约束选择适合在正交频分复用（OFDM）数据传输设备中使用的音调。这些约束包括可用音调的数量，调制类型和码率。 OFDM设备可以使用有线或无线传输。

82. 发明授权

US07940853B2 Method and device for calculating zero-croccing reference sequences for signal detection of angle-modulated signals based on zero crossings of the received signal 失效
标题翻译：用于计算过零参考序列的方法和装置，用于基于接收信号的过零点的角度调制信号的信号检测
公开(公告)号：US07940853B2
公开(公告)日：2011-05-10
申请号：US12358255
申请日：2009-01-23
申请人： Juergen Niederholz , Andre Neubauer
发明人： Juergen Niederholz , Andre Neubauer
IPC分类号： H04L27/10
CPC分类号： H04L27/2337
摘要： A method for calculating zero-crossing reference sequences ({ti}) for the data detection of a sequence of zero crossings ({{circumflex over (t)}i}) of a received signal is disclosed. The data detection is determined in a receiver, wherein the received signal is based on a data symbol sequence ({dk}) angle-modulated at a transmitter and transmitted to the receiver. The zero-crossing reference sequences ({ti}) are calculated in accordance with an equation specifying an output of a finite state machine that describes, at least approximately, the signal generation in the transmitter.
摘要翻译：公开了一种用于计算过零参考序列（{ti}）的方法，用于对接收信号的过零序列（{{circumflex over（t）} i}）进行数据检测。在接收机中确定数据检测，其中所接收的信号基于在发射机处角度调制并被发送到接收机的数据符号序列（{dk}）。过零参考序列（{ti}）根据指定有限状态机的输出的等式来计算，该有限状态机的输出至少近似地描述了发射机中的信号产生。

83. 发明授权

US07933354B2 Encoding and decoding architecture and method for pipelining encoded data or pipelining with a look-ahead strategy 有权
标题翻译：编码和解码结构和方法，用于流水线编码数据或流水线与预先策略
公开(公告)号：US07933354B2
公开(公告)日：2011-04-26
申请号：US11641363
申请日：2006-12-18
申请人： Samuel A. Steidl , Peter F. Curran
发明人： Samuel A. Steidl , Peter F. Curran
IPC分类号： H04L27/10
CPC分类号： H04L27/2075
摘要： An encoding and/or decoding communication system comprises a framer interface, an encoder, a multiplexer, an output driver, and a clock multiplier unit (CMU). The encoder includes an input latch circuitry stage; an output latch circuitry stage; an intermediate latch circuitry stage interposed between the input latch circuitry stage and the output latch circuitry stage, the intermediate latch circuitry stage coupled to the input latch circuitry stage and the output latch circuitry stage; a plurality of encoding logic circuitry stages interposed between the input latch circuitry stage and the output latch circuitry stage, a last one of the plurality of encoding logic circuitry stages placed adjacent to the output latch circuitry stage and coupled to the output latch circuitry stage; and a feedback between the output latch circuitry stage and the last one of the plurality of encoding logic circuitry stages.
摘要翻译：编码和/或解码通信系统包括成帧器接口，编码器，多路复用器，输出驱动器和时钟倍增器单元（CMU）。编码器包括输入锁存电路级; 输出锁存电路级; 插入在输入锁存电路级和输出锁存电路级之间的中间锁存电路级，中间锁存电路级耦合到输入锁存电路级和输出锁存电路级; 插入在输入锁存电路级和输出锁存电路级之间的多个编码逻辑电路级，多个编码逻辑电路级中的最后一个与输出锁存电路级放置并耦合到输出锁存电路级; 以及输出锁存电路级与多个编码逻辑电路级中的最后一个之间的反馈。

84. 发明授权

US07864900B2 Communication system for sending and receiving digital data 有权
标题翻译：用于发送和接收数字数据的通信系统
公开(公告)号：US07864900B2
公开(公告)日：2011-01-04
申请号：US11554204
申请日：2006-10-30
申请人： Abdullah A. Al-Eidan
发明人： Abdullah A. Al-Eidan
IPC分类号： H04L27/10
CPC分类号： H04L27/10 , H04L27/2626 , H04L27/2647
摘要： A system and method for constructing a transmitter and a receiver that communicate using multiple orthogonal frequencies which are locked to each other. The set of available frequencies can range from 7, 32 frequencies to a much larger set of frequencies. The transmitted frequencies are separated by a small limited bandwidth (B.W). multiple frequencies are selected from a set of available frequencies and transmitted simultaneously to the receiver. The data transmission is preceded by a calibration sequence where the shift between the transmitted frequency and the frequency measured by fast Fourier transform at the receiver system contain encoders and decoders that convert binary numbers to frequency combinations and the reverse. This transceiver system is capable of transmitting large data rate per unit of a bandwidth e.g. 6 Mbps/3.2 MHZ.
摘要翻译：一种用于构建使用彼此锁定的多个正交频率进行通信的发射机和接收机的系统和方法。可用频率的范围可以从7,32个频率到更大的一组频率。传输的频率由小的有限带宽（B.W）分隔开。从一组可用频率中选择多个频率并同时传送到接收机。数据传输之前是校准序列，其中在接收机系统处通过快速傅里叶变换测量的发射频率和频率之间的偏移包含将二进制数转换成频率组合的编码器和解码器，反之亦然。该收发器系统能够传送每单位带宽的大数据速率，例如， 6 Mbps / 3.2 MHZ。

85. 发明授权

US07835460B2 Apparatus and methods for reducing channel estimation noise in a wireless transceiver 有权
标题翻译：用于降低无线收发器中的信道估计噪声的装置和方法
公开(公告)号：US07835460B2
公开(公告)日：2010-11-16
申请号：US11303485
申请日：2005-12-15
申请人： Michael Mao Wang
发明人： Michael Mao Wang
IPC分类号： H04L27/10
CPC分类号： H04L25/0216 , H04L27/2647
摘要： Apparatus and methods for use in a wireless communication system are disclosed for reducing channel estimation noise in a device such as a wireless transceiver. A disclosed apparatus includes a processor that determines a channel activity portion and a noise portion of a channel estimation. The processor also determines a threshold noise level based on channel estimate values in the noise portion of the channel estimation. The processor compares channel estimate energy values in the channel estimation to the threshold noise level and sets each of the channel estimate energy values being less than the threshold noise level to a predetermined value such as zero in order to reduce or eliminate the noise. Similar methods are also disclosed.
摘要翻译：公开了用于无线通信系统中的装置和方法，用于减少诸如无线收发器之类的装置中的信道估计噪声。所公开的装置包括确定信道估计的信道活动部分和噪声部分的处理器。处理器还基于信道估计的噪声部分中的信道估计值来确定阈值噪声电平。处理器将信道估计中的信道估计能量值与阈值噪声电平进行比较，并将每个信道估计能量值小于阈值噪声电平设置为诸如零的预定值，以便减少或消除噪声。还公开了类似的方法。

86. 发明授权

US07751497B2 Method to minimize compatibility error in hierarchical modulation using variable phase 有权
标题翻译：使用可变相分级调制最小化兼容性错误的方法
公开(公告)号：US07751497B2
公开(公告)日：2010-07-06
申请号：US11474735
申请日：2006-06-26
申请人： Glenn A. Walker , Eric A. Dibiaso , Michael L. Hiatt, Jr.
发明人： Glenn A. Walker , Eric A. Dibiaso , Michael L. Hiatt, Jr.
IPC分类号： H04L27/20 , H04L27/10 , H04L27/00 , H04L9/00 , H04K1/10 , H04J11/00
CPC分类号： H04B7/18513 , H04L27/183 , H04L27/3488
摘要： The present invention provides a method, receiver and transmitter for use in a SDAR system. The method involves generating a first modulated signal based on first input data. Additional modulation is superimposed on the first modulated signal based on additional input data, being spread across a plurality of symbols in the first modulated signal in a predetermined pattern to generate a modified signal which is then transmitted. The modified signal is decoded by performing a first demodulation of the first modulated signal then additional demodulation is performed to obtain additional input data. The superimposing step uses a plurality of offset sequence values to add the additional modulation to the first modulated signal. The offset sequence may appear as a pseudo-random distribution of offset sequence values, and may include at least one zero offset value. Alternatively, the additional modulated signal may be a formed as a direct sequence spread spectrum modulation and the offset sequence appearing as a pseudo-noise distribution. A Hadamard matrix sequence may be used as the direct sequence code.
摘要翻译：本发明提供一种用于SDAR系统的方法，接收机和发射机。该方法包括基于第一输入数据产生第一调制信号。基于额外的输入数据将附加调制叠加在第一调制信号上，以预定模式扩展到第一调制信号中的多个符号，以产生随后发送的经修改的信号。通过执行第一调制信号的第一解调来解码修改的信号，然后执行附加解调以获得附加的输入数据。叠加步骤使用多个偏移序列值将附加调制附加到第一调制信号。偏移序列可以显示为偏移序列值的伪随机分布，并且可以包括至少一个零偏移值。或者，附加调制信号可以形成为直接序列扩频调制，并且出现作为伪噪声分布的偏移序列。可以使用Hadamard矩阵序列作为直接序列码。

87. 发明授权

US07649956B2 Modulation and demodulation system, modulator, demodulator and phase modulation method and phase demodulation method used therefor 失效
标题翻译：调制解调系统，调制器，解调器和相位调制方法及相位解调方法
公开(公告)号：US07649956B2
公开(公告)日：2010-01-19
申请号：US11255577
申请日：2005-10-21
申请人： Seiichi Noda , Shinichi Koike
发明人： Seiichi Noda , Shinichi Koike
IPC分类号： H04L27/10 , H04L27/18
CPC分类号： H04L27/186 , H04L25/4923 , H04L27/18
摘要： A modulation and demodulation system capable of minimizing a bit error rate in a six-phase phase modulation method. A senary signal phase-modulated and outputted by a modulator is received and phase-modulated by a destination demodulator to a binary signal before conversion by the modulator. The modulator assigns (0, 0), (0, 1), (0, 2), (1, 2), (1, 1) and (1, 0) which are senary signals (bi, ti) to first to sixth phases respectively. The demodulator performs a conversion process from the senary signals to the binary signals, for instance, by storing transmitted senary signals and sequentially converting every senary signal of length m to binary signal of length b so as to output them. The process of the demodulator assigns the first to sixth phases as the senary signals (bi, ti) to (0, 0), (0, 1), (0, 2), (1, 2), (1, 1) and (1, 0) respectively.
摘要翻译：一种能够最小化六相相位调制方法中的误比特率的调制和解调系统。在由调制器转换之前，由调制器相位调制和输出的信号信号被目的地解调器接收并被相位调制为二进制信号。调制器将作为参数信号（bi，ti）的（0,0），（0,1），（0,2），（1,2），（1,1）和（1,0）分别分配给第六阶段。解调器执行从参数信号到二进制信号的转换处理，例如通过存储发送的信号信号并将长度为m的每个参数信号顺序地转换为长度为b的二进制信号，以便输出它们。解调器的过程将第一至第六相分配为参数信号（bi，ti）至（0,0），（0,1），（0,2），（1,2），（1,1）和（1,0）。

88. 发明授权

US07447277B2 Ofdm demodulation device 失效
标题翻译： Ofdm解调装置
公开(公告)号：US07447277B2
公开(公告)日：2008-11-04
申请号：US10504341
申请日：2003-12-18
申请人： Atsushi Yajima , Kazuhisa Funamoto , Yasunari Ikeda
发明人： Atsushi Yajima , Kazuhisa Funamoto , Yasunari Ikeda
IPC分类号： H04L27/00 , H04L27/10 , H03K7/06
CPC分类号： H04L27/2605 , H04L7/02 , H04L27/2662 , H04L27/2676
摘要： An OFDM receiver (1) is provided which includes a clock-frequency error calculation circuit (41) to calculate a difference in clock frequency between a clock for a received signal and an operation clock used in the receiver (1), and a guard correlation/peak detection circuit (12) to determine an autocorrelation of a guard interval and detect a peak timing of the correlation signal. The guard correlation/peak detection circuit (12) incorporates a free-running counter, and outputs a count of the free-running counter at the peak timing to the clock-frequency error calculation circuit (41). The clock-frequency error calculation circuit (41) uses a plurality of time-change rate detection circuits provided at different time intervals to calculate a time-change rate of an input count. The clock-frequency error calculation circuit (41) plots the time-change rates to generate a histogram and calculates a clock-frequency error from the histogram.
摘要翻译：提供了一种OFDM接收器（1），其包括时钟频率误差计算电路（41），用于计算接收信号的时钟和接收机（1）中使用的操作时钟之间的时钟频率差，以及保护相关 /峰值检测电路（12），以确定保护间隔的自相关性并检测相关信号的峰值定时。保护相关/峰值检测电路（12）包含自由运行计数器，并将峰值定时的自由运行计数器的计数输出到时钟频率误差计算电路（41）。时钟频率误差计算电路（41）使用以不同时间间隔设置的多个时变速率检测电路来计算输入计数的时间变化率。时钟频率误差计算电路（41）绘制时间变化率以产生直方图，并根据直方图计算时钟频率误差。

89. 发明授权

US07369623B2 Apparatuses to simultaneously distribute clock signals and data on integrated circuits, interposers, and circuit boards 有权
标题翻译：在集成电路，插入器和电路板上同时分配时钟信号和数据的装置
公开(公告)号：US07369623B2
公开(公告)日：2008-05-06
申请号：US11594480
申请日：2006-11-08
申请人： Leonard Forbes
发明人： Leonard Forbes
IPC分类号： H04L27/10
CPC分类号： H03K5/15013 , H04L7/0008 , H04L27/18 , H04L27/22
摘要： A technique is described for simultaneously and synchronously transmitting digital data and a clock signal in a digital integrated circuit, circuit board, or system. The technique is based on the phase shift keying (PSK) modulation of an RF high frequency carrier which is distributed on low impedance interconnection transmission lines. The PSK modulation contains the digital data while the carrier itself constitutes the clock signal, and the clock signal and digital data are transmitted in a synchronous manner. The carrier frequency may be near fT, the maximum operation frequency of the transistors. Since the digital data and clock signal are simultaneously transmitted on the same interconnection, the digital data never becomes skewed with respect to the clock signal, or vice versa.
摘要翻译：描述了用于在数字集成电路，电路板或系统中同时和同步地发送数字数据和时钟信号的技术。该技术基于分布在低阻抗互连传输线上的RF高频载波的相移键控（PSK）调制。 PSK调制包含数字数据，而载波本身构成时钟信号，时钟信号和数字数据以同步方式传输。载波频率可以接近晶体管的最大工作频率。由于数字数据和时钟信号在相同的互连上同时发送，所以数字数据不会相对于时钟信号变得倾斜，反之亦然。

90. 发明申请

US20080076355A1 Method for Protecting Security Accounts Manager (SAM) Files Within Windows Operating Systems 有权
标题翻译：在Windows操作系统中保护安全帐户管理器（SAM）文件的方法
公开(公告)号：US20080076355A1
公开(公告)日：2008-03-27
申请号：US11535542
申请日：2006-09-27
申请人： Rod D. Waltermann , David C. Challener , Philip L. Childs , Norman A. Dion , James Hunt , Nathan J. Peterson , David Rivera , Randall S. Springfield , Arnold S. Weksler
发明人： Rod D. Waltermann , David C. Challener , Philip L. Childs , Norman A. Dion , James Hunt , Nathan J. Peterson , David Rivera , Randall S. Springfield , Arnold S. Weksler
IPC分类号： H04B1/00 , H04B7/00 , H03K7/06 , H04L27/10 , H04B1/26 , H04B1/06 , H03K9/06 , H04B15/00
CPC分类号： G06F21/575 , G06F21/6209 , G06F2221/2107 , H04L9/0897 , H04L2209/127
摘要： A method for protecting Security Accounts Manager (SAM) files within a Windows® operating system is disclosed. A SAM file encryption key is generated by encrypting a SAM file via a syskey utility provided within the Windows® operating system. The SAM file encryption key is then stored in a virtual floppy disk by selecting an option to store SAM file encryption key to a floppy disk under the syskey utility. A blob is generated by performing a Trusted Platform Module (TPM) Seal command against the SAM file encryption key along with a value stored in a Performance Control Register and a TPM Storage Root Key. The blob is stored in a non-volatile storage area of a computer.
摘要翻译：公开了一种在Windows（R）操作系统中保护安全帐户管理器（SAM）文件的方法。通过Windows（R）操作系统中提供的syskey实用程序加密SAM文件来生成SAM文件加密密钥。然后，SAM文件加密密钥存储在虚拟软盘中，方法是选择将SAM文件加密密钥存储到syskey实用程序下的软盘中。通过对SAM文件加密密钥执行可信平台模块（TPM）密封命令以及存储在性能控制寄存器和TPM存储根密钥中的值来生成blob。斑点存储在计算机的非易失性存储区域中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式