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1. 发明申请

US20180254929A1 METHOD AND DEVICE FOR TRANSMITTING PAY LOAD SEQUENCE 审中-公开
公开(公告)号：US20180254929A1
公开(公告)日：2018-09-06
申请号：US15971825
申请日：2018-05-04
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Chang Soon PARK , Young Jun HONG , Sujit JOS , Young Soo KIM , Chandrashekhar Thejaswi PS , Kiran BYNAM , Manoj CHOUDHARY
IPC分类号： H04L25/03 , H04L27/04 , H04B1/709 , H04L25/49
CPC分类号： H04L25/03834 , H04B1/709 , H04B1/71637 , H04L25/03312 , H04L25/4923 , H04L27/04
摘要： A method and a transmitter for transmitting a pay load sequence are provided. The transmitter includes a ternary sequence mapper configured to map a binary data sequence to a ternary sequence stored in the transmitter, and a pulse shaping filter configured to generate a first signal based on the mapped ternary sequence. The ternary sequence includes elements of −1, 0, and 1

2. 发明申请

US20180062887A1 USING FULL TERNARY TRANSCODING IN I3C HIGH DATA RATE MODE 审中-公开
公开(公告)号：US20180062887A1
公开(公告)日：2018-03-01
申请号：US15659408
申请日：2017-07-25
申请人： QUALCOMM Incorporated
发明人： Shoichiro SENGOKU
IPC分类号： H04L25/49 , H04L7/00
CPC分类号： H04L25/4923 , G06F13/4291 , H03M13/09 , H04L7/0037 , H04L7/0087 , H04L25/14 , H04L25/4906
摘要： Apparatus, systems and methods for improving coexistence on a multi-wire interface are disclosed. A method of transmitting data on a multi-wire interface includes providing a plurality of data bits in a word to be transmitted on the multi-wire interface, transcoding the word to be transmitted to obtain a first multi-digit ternary number representative of the numerical value of the word to be transmitted, inserting marker digits into the first multi-digit ternary number to obtain a second multi-digit ternary number, and generating a sequence of symbols. Each symbol in the sequence of symbols may be generated using a digit of the second multi-digit ternary number and a preceding symbol in the sequence of symbols. The preconfigured values and the preconfigured locations of the marker digits may be selected to prevent occurrence of I3C HDR Exit or HDR I3C Restart signaling when the sequence of symbols is transmitted on the multi-wire interface.

3. 发明授权

US09819523B2 Intelligent equalization for a three-transmitter multi-phase system 有权
公开(公告)号：US09819523B2
公开(公告)日：2017-11-14
申请号：US15453352
申请日：2017-03-08
申请人： QUALCOMM Incorporated
发明人： Chulkyu Lee , Shih-Wei Chou , George Wiley
IPC分类号： H04K1/02 , H04L25/03 , H04L25/49 , H04B7/06
CPC分类号： H04L25/4917 , H04B7/0682 , H04L25/0272 , H04L25/03343 , H04L25/03878 , H04L25/14 , H04L25/4923
摘要： An intelligent equalization technique is provided for a three-transmitter system in which mid-level transitions are selectively emphasized and de-emphasized to conserve power and reduce data jitter.

4. 发明申请

US20170264471A1 INTELLIGENT EQUALIZATION FOR A THREE-TRANSMITTER MULTI-PHASE SYSTEM 有权
公开(公告)号：US20170264471A1
公开(公告)日：2017-09-14
申请号：US15453352
申请日：2017-03-08
申请人： QUALCOMM Incorporated
发明人： Chulkyu Lee , Shih-Wei Chou , George Wiley
IPC分类号： H04L25/49 , H04L25/03 , H04B7/06
CPC分类号： H04L25/4917 , H04B7/0682 , H04L25/0272 , H04L25/03343 , H04L25/03878 , H04L25/14 , H04L25/4923
摘要： An intelligent equalization technique is provided for a three-transmitter system in which mid-level transitions are selectively emphasized and de-emphasized to conserve power and reduce data jitter.

5. 发明申请

US20170085466A1 DATA TRANSMISSION APPARATUS, DATA RECEPTION APPARATUS, DATA TRANSMISSION AND RECEPTION SYSTEM 有权
公开(公告)号：US20170085466A1
公开(公告)日：2017-03-23
申请号：US15245514
申请日：2016-08-24
申请人： SK hynix Inc. , POSTECH ACADEMY-INDUSTRY FOUNDATION
发明人： Hong June PARK , Soo MIn LEE , Yong Ju KIM , Hae Kang JUNG
IPC分类号： H04L12/707
CPC分类号： H04L45/24 , G06F13/38 , G11C5/066 , G11C7/02 , G11C7/10 , G11C7/1006 , G11C11/4093 , H04B1/40 , H04B3/32 , H04B15/005 , H04L1/00 , H04L25/0274 , H04L25/08 , H04L25/4917 , H04L25/4919 , H04L25/4923
摘要： A data transmission and reception system may include: a data transmission apparatus configured to generate N Tx signals having discrete levels using N binary data, and output the N Tx signals to N single-ended signal lines, respectively, where N is a natural number equal to or larger than 2; and a data reception apparatus configured to receive the N Tx signals transmitted in parallel through the single-ended signal lines, and restore the N binary data by comparing the received N Tx signals to each other.

6. 发明申请

US20170063579A1 METHOD AND DEVICE FOR TRANSMITTING PAY LOAD SEQUENCE 有权
标题翻译：用于发送支付负载序列的方法和装置
公开(公告)号：US20170063579A1
公开(公告)日：2017-03-02
申请号：US15033352
申请日：2014-10-29
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Chang Soon PARK , Young Jun HONG , Sujit JOS , Young Soo KIM , Chandrashekhar Thejaswi PS , Kiran BYNAM , Manoj CHOUDHARY
IPC分类号： H04L25/03 , H04L27/04 , H04B1/709
CPC分类号： H04L25/03834 , H04B1/709 , H04L25/03312 , H04L25/4923 , H04L27/04
摘要： The present invention relates to a method and a device for transmitting a pay load sequence, and provides in one embodiment a transmitter comprising a first signal converter for converting a ternary payload sequence composed of elements −1, 0, or 1 into a first signal, wherein the first signal converter comprises: a ternary sequence mapper for generating the ternary payload sequence by mapping a pre-designed sequence into a binary data sequence; and a converter for converting the ternary payload sequence into the first signal.
摘要翻译：本发明涉及一种用于发送付费负载序列的方法和装置，并且在一个实施例中提供一种发射机，其包括用于将由元素-1,0或1组成的三元有效载荷序列转换为第一信号的第一信号转换器，其中所述第一信号转换器包括：三进制序列映射器，用于通过将预先设计的序列映射成二进制数据序列来产生所述三进制有效载荷序列; 以及用于将三进制有效载荷序列转换为第一信号的转换器。

7. 发明申请

US20160323056A1 METHOD AND DEVICE FOR TRANSMITTING PREAMBLE SEQUENCE 审中-公开
标题翻译：用于发送前缀序列的方法和设备
公开(公告)号：US20160323056A1
公开(公告)日：2016-11-03
申请号：US15033400
申请日：2014-10-30
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Chang Soon PARK , Young Jun HONG , Jinesh P NAIR , Joon Seong KANG , Young Soo KIM , Sujit JOS , Manoj CHOUDHARY
IPC分类号： H04J13/16 , H04L25/49
CPC分类号： H04J13/16 , H04B1/0475 , H04B1/7097 , H04B2201/70707 , H04B2201/709709 , H04J13/0011 , H04J13/0022 , H04J13/0044 , H04J13/10 , H04J13/107 , H04L1/247 , H04L25/4923 , H04L27/04 , H04L27/233 , H04L27/2627 , H04L27/2692 , H04L27/36 , H04L27/38
摘要： A method and device for transmitting a preamble sequence is disclosed. A transmitter according to an embodiment may extract a first sequence for a non-coherent receiver and a second sequence for a coherent receiver, from ternary preamble sequences including elements −1, 0 and 1, and map the first sequence and the second sequence to a preamble including a plurality of bits to generate a third sequence that the non-coherent receiver and coherent receiver support.
摘要翻译：公开了一种用于发送前置码序列的方法和装置。根据实施例的发射机可以从包括元素-1,0和1的三进位序列序列中提取非相干接收机的第一序列和相干接收机的第二序列，并将第一序列和第二序列映射到前导码包括多个位以产生非相干接收机和相干接收机支持的第三序列。

8. 发明授权

US09485080B1 Multiphase clock data recovery circuit calibration 有权
标题翻译：多相时钟数据恢复电路校准
公开(公告)号：US09485080B1
公开(公告)日：2016-11-01
申请号：US14842610
申请日：2015-09-01
申请人： QUALCOMM Incorporated
发明人： Ying Duan , Chulkyu Lee , Harry Dang , Ohjoon Kwon
IPC分类号： H04L7/00 , H04L5/00 , H04L7/08
CPC分类号： H04L7/0008 , H03K5/135 , H04L5/0048 , H04L7/033 , H04L7/04 , H04L7/08 , H04L25/0272 , H04L25/4923
摘要： Methods, apparatus, and systems for clock calibration are disclosed. A method for clock data recovery circuit calibration includes configuring a first clock recovery circuit to provide a clock signal that has a first frequency and that includes a single pulse for each symbol transmitted on a 3-wire, 3-phase interface, and calibrating the first clock recovery circuit by incrementally increasing a delay period provided by a delay element of the first clock recovery circuit until the clock signal provided by the first clock recovery circuit has a frequency that is less than the first frequency and, when the first clock recovery circuit has a frequency that is less than the first frequency, incrementally decreasing the delay period provided by the delay element of the first clock recovery circuit until the clock signal provided by the first clock recovery circuit has a frequency that matches the first frequency.
摘要翻译：公开了用于时钟校准的方法，装置和系统。一种用于时钟数据恢复电路校准的方法包括配置第一时钟恢复电路以提供具有第一频率的时钟信号，并且对于在3线3相接口上传输的每个符号包括单个脉冲，并且校准第一频率时钟恢复电路，通过逐渐增加由第一时钟恢复电路的延迟元件提供的延迟时间，直到由第一时钟恢复电路提供的时钟信号具有小于第一频率的频率，并且当第一时钟恢复电路具有小于第一频率的频率，逐渐减小由第一时钟恢复电路的延迟元件提供的延迟周期，直到由第一时钟恢复电路提供的时钟信号具有与第一频率匹配的频率。

9. 发明授权

US09473291B2 Apparatuses and methods for reducing switching jitter 有权
标题翻译：减少开关抖动的装置和方法
公开(公告)号：US09473291B2
公开(公告)日：2016-10-18
申请号：US14325837
申请日：2014-07-08
申请人： Intel Corporation
发明人： Jonggab Kil
IPC分类号： H04J3/06 , H04L7/00 , H04L25/14 , H04L25/49
CPC分类号： H04L7/0041 , H04L7/0091 , H04L25/14 , H04L25/49 , H04L25/4923
摘要： Described are apparatuses and methods for reducing channel physical layer (C-PHY) switching jitter. An apparatus may include a pattern dependent delay circuit to detect a switching pattern of at least three data signals on respective wires and adaptively change delays of the at least three data signals based on the switching pattern. The apparatus may further include a transmitter, coupled to the pattern dependent delay circuit, to transmit the at least three data signals.
摘要翻译：描述了用于减少信道物理层（C-PHY）切换抖动的装置和方法。装置可以包括模式相关延迟电路，以检测相应线路上的至少三个数据信号的切换模式，并且基于切换模式自适应地改变至少三个数据信号的延迟。该装置还可以包括耦合到模式相关延迟电路的发送器，以发送至少三个数据信号。

10. 发明授权

US09154156B2 Ternary line code design for controlled decision feedback equalizer error propagation 有权
标题翻译：用于受控决策反馈均衡器误差传播的三元线代码设计
公开(公告)号：US09154156B2
公开(公告)日：2015-10-06
申请号：US14335357
申请日：2014-07-18
申请人： QUALCOMM Incorporated
发明人： Xiao Feng Wang , Stephen Jay Shellhammer
IPC分类号： H03M5/16 , H04L25/49 , H03M7/46 , H03M5/14
CPC分类号： H03M5/16 , H03M5/145 , H03M7/46 , H04L25/03057 , H04L25/49 , H04L25/4923
摘要： A method of line coding is disclosed that limits error propagation in a decision feedback equalizer (DFE) of a receiving device. A communications device receives a set of bits to be transmitted over a channel and divides the set of bits into a plurality of blocks based, at least in part, on a line coding scheme. The device then encodes each of the blocks of bits into a corresponding block of symbols based on the line coding scheme. Specifically, the line coding scheme has a non-uniform coding efficiency, wherein a first bit or a last bit of each block of bits is mapped to a single data symbol. For some embodiments, the line coding scheme may be a ternary line coding scheme that maps a block of 3k+1 bits to a corresponding block of 2k+1 symbols, where k is an integer greater than 1.
摘要翻译：公开了一种限制接收设备的判决反馈均衡器（DFE）中的误差传播的线路编码方法。通信设备接收要通过信道发送的一组比特，并且至少部分地基于线路编码方案将比特集合分成多个块。然后，该设备基于线路编码方案将每个比特块块编码成相应的符号块。具体地，线路编码方案具有不均匀的编码效率，其中每个比特块的第一比特或最后一比特被映射到单个数据符号。对于一些实施例，线路编码方案可以是将3k + 1比特的块映射到2k + 1个符号的对应块的三元线编码方案，其中k是大于1的整数。

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