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81. 发明申请

US20050281091A1 Fast memory 有权
标题翻译：快速记忆
公开(公告)号：US20050281091A1
公开(公告)日：2005-12-22
申请号：US11157133
申请日：2005-06-20
申请人： Jean-Pierre Schoellkopf
发明人： Jean-Pierre Schoellkopf
IPC分类号： G11C8/16 , G11C11/413 , G11C7/10
CPC分类号： G11C8/16 , G11C11/413
摘要： A storage circuit using a dual-access memory, comprising means for alternately activating one access, then the other, with a maximum frequency equal to twice the maximum possible frequency of activation of a given access, at least two successive activations of said means controlling operations of the same type, reading or writing.
摘要翻译：一种使用双重存取存储器的存储电路，包括用于以最大频率等于给定存取的激活的最大可能频率的两倍的方式交替地激活一个存取的装置，另一个存储装置，所述装置控制操作的至少两次连续激活相同类型，阅读或写作。

82. 发明申请

US20050265095A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20050265095A1
公开(公告)日：2005-12-01
申请号：US11114165
申请日：2005-04-26
申请人： Norihiko Sumitani , Masaya Sumita
发明人： Norihiko Sumitani , Masaya Sumita
IPC分类号： G11C11/41 , G11C7/00 , G11C7/06 , G11C7/12 , G11C7/18 , G11C11/413 , H01L27/02
CPC分类号： G11C11/413 , G11C7/065 , G11C7/12 , G11C7/18 , G11C2207/005
摘要： Voltage transfer switches and voltage input/output circuits are provided on a complementary bus line pair to be shared among a plurality of columns of a memory cell array. After a complementary bit line pair is precharged to a predetermined voltage, the voltage of uninverted bit line and the voltage of inverted bit line are exchanged before any of all memory cells belonging to the same column is selected by a word line. With this structure, a predetermined potential difference is ensured between the complementary bit line pair at the time of an activation of a sense amplifier even if the total sum of the off-leak currents of access transistors in all the memory cells belonging to the same column is almost as large as the ON-current (drive current) of a single drive transistor.
摘要翻译：电压转换开关和电压输入/输出电路设置在互补总线对上，以在存储单元阵列的多个列之间共享。在将互补位线对预充电至预定电压之后，在通过字线选择属于同一列的所有存储单元中的任何一个之前，交换未反相位线的电压和反相位线的电压。利用这种结构，即使在属于同一列的所有存储单元中的存取晶体管的漏电电流的总和与激活感测放大器时互补位线对之间也保证了预定的电位差几乎与单个驱动晶体管的导通电流（驱动电流）一样大。

83. 发明授权

US06967861B2 Method and apparatus for improving cycle time in a quad data rate SRAM device 有权
标题翻译：用于改善四倍数据速率SRAM器件中的周期时间的方法和装置
公开(公告)号：US06967861B2
公开(公告)日：2005-11-22
申请号：US10708379
申请日：2004-02-27
申请人： George M. Braceras , Harold Pilo
发明人： George M. Braceras , Harold Pilo
IPC分类号： G11C8/00 , G11C11/00 , G11C11/413
CPC分类号： G11C11/413
摘要： A method for implementing a self-timed, read to write operation in a memory storage device. In an exemplary embodiment, the method includes capturing a read address during a first half of a current clock cycle, and commencing a read operation so as to read data corresponding to the captured read address onto a pair of bit lines. A write operation is commenced for the current clock cycle so as to cause write data to appear on the pair of bit lines as soon as the read data from the captured read address is amplified by a sense amplifier, wherein the write operation uses a previous write address captured during a preceding clock cycle. A current write address is captured during a second half of the current clock cycle, said current write address used for a write operation implemented during a subsequent clock cycle, wherein the write operation for the current clock cycle is timed independent of the current write address captured during said second half of the current clock cycle.
摘要翻译：一种用于在存储器存储设备中实现自定时的读写操作的方法。在一个示例性实施例中，该方法包括在当前时钟周期的前半部分期间捕获读取地址，并开始读取操作，以便将对应于所捕获的读取地址的数据读取到一对位线上。一旦当前时钟周期开始写入操作，以便一旦来自捕获的读取地址的读取数据被读出放大器放大，就会使写入数据出现在该对位线上，其中写入操作使用先前的写入在前一个时钟周期捕获的地址。在当前时钟周期的后半段期间捕获当前写入地址，所述当前写入地址用于在随后的时钟周期期间实现的写入操作，其中当前时钟周期的写入操作被独立于捕获的当前写入地址在当前时钟周期的后半段。

84. 发明申请

US20050249017A1 Semiconductor device having a power down mode 有权
公开(公告)号：US20050249017A1
公开(公告)日：2005-11-10
申请号：US11183802
申请日：2005-07-19
申请人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
发明人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
IPC分类号： G11C11/413 , G11C5/06 , G11C5/14 , G11C7/10 , G11C8/00 , G11C8/12 , G11C11/401 , G11C11/406 , G11C11/407 , G11C11/4074 , G11C11/4076 , G11C11/409 , H01L21/8242 , H01L27/108
CPC分类号： G11C5/063 , G11C5/14 , G11C5/147 , G11C7/1072 , G11C8/12 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2211/4067 , G11C2211/4068
摘要： A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

85. 发明申请

US20050225379A1 Internal voltage generation circuit of semiconductor memory device 审中-公开
标题翻译：半导体存储器件的内部电压产生电路
公开(公告)号：US20050225379A1
公开(公告)日：2005-10-13
申请号：US10982165
申请日：2004-11-05
申请人： Jae-Hyuk Im , Jae-Jin Lee
发明人： Jae-Hyuk Im , Jae-Jin Lee
IPC分类号： G11C5/14 , G11C7/00 , G11C11/4063 , G11C11/4074 , G11C11/413 , H03L5/00
CPC分类号： G11C5/14 , G11C11/406 , G11C11/4074 , G11C2211/4068
摘要： Disclosed herein is an internal voltage generation circuit of a semiconductor memory device which is capable of supplying voltages of different levels to a column path & control logic and data path & control logic in the memory device according to different operation modes of the memory device. The column path & control logic and data path & control logic are applied with a normal operating voltage when they are involved in the current operation mode of the memory device, whereas with a lower voltage when they are not involved. Therefore, the present invention has the effect of efficiently managing internal voltages of the semiconductor memory device and reducing current leakage of the memory device and, in turn, unnecessary power consumption thereof.
摘要翻译：本文公开了一种半导体存储器件的内部电压产生电路，其能够根据存储器件的不同操作模式向存储器件中的列路径和控制逻辑以及数据路径和控制逻辑提供不同电平的电压。列路径和控制逻辑以及数据路径和控制逻辑在其参与存储器件的当前操作模式时被应用于正常工作电压，而当它们不涉及时具有较低的电压。因此，本发明具有有效地管理半导体存储器件的内部电压并且减少存储器件的电流泄漏的效果，并且反过来又导致其不必要的功耗。

86. 发明申请

US20050218965A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20050218965A1
公开(公告)日：2005-10-06
申请号：US11144695
申请日：2005-06-06
申请人： Hiroyuki Mizuno , Koichiro Ishibashi , Takanori Shimura , Toshihiro Hattori
发明人： Hiroyuki Mizuno , Koichiro Ishibashi , Takanori Shimura , Toshihiro Hattori
IPC分类号： G11C11/413 , G11C5/14 , G11C11/408 , H01L21/822 , H01L23/58 , H01L27/02 , H01L27/04 , H01L27/092
CPC分类号： H01L27/0207 , G11C5/14 , G11C5/146 , G11C5/147 , H01L27/0928 , H01L27/11807 , H01L2924/0002 , H03K19/0016 , H01L2924/00
摘要： In order to provide a semiconductor IC unit such as a microprocessor, etc., which satisfies both fast operation and lower power consumption properties with its high quality kept, the semiconductor IC unit of the present invention is composed so as to include a main circuit (LOG) provided with transistors, which is formed on a semiconductor substrate, and a substrate bias controlling circuit (VBC) used for controlling a voltage to be applied to the substrate, and the main circuit includes switching transistors (MN1 and MP1) used for controlling a voltage to be applied to the substrate and control signals output from the substrate bias controlling circuit is entered to the gate of each of the switching transistors and the control signal is returned to the substrate bias controlling circuit.
摘要翻译：为了提供满足快速操作和低功耗特性的诸如微处理器等的半导体IC单元，保持其高质量，本发明的半导体IC单元被构成为包括主电路（ LOG），其形成在半导体衬底上的晶体管和用于控制施加到衬底的电压的衬底偏置控制电路（VBC），并且主电路包括使用的开关晶体管（MN 1和MP 1）用于控制施加到衬底的电压，并且从衬底偏置控制电路输出的控制信号被输入到每个开关晶体管的栅极，并且控制信号返回到衬底偏置控制电路。

87. 发明申请

US20050213404A1 Semiconductor memory device and precharge control method 失效
标题翻译：半导体存储器件和预充电控制方法
公开(公告)号：US20050213404A1
公开(公告)日：2005-09-29
申请号：US10943002
申请日：2004-09-17
申请人： Tsuyoshi Kodama
发明人： Tsuyoshi Kodama
IPC分类号： G11C11/41 , G11C7/00 , G11C7/12 , G11C11/4063 , G11C11/4094 , G11C11/413 , G11C11/416 , H01L27/108 , H01L27/11
CPC分类号： G11C11/413 , G11C7/12
摘要： A semiconductor memory device that quickly precharges a bit line and shortens the cycle time for accessing the memory cells. The semiconductor memory device includes a memory cell array having a plurality of memory cells. A bit line is connected to the plurality of memory cells. A plurality of precharge circuits are connected to the bit line to precharge the bit line to a predetermined potential. A timing control circuit generates a timing signal. The precharge control circuit controls the precharge circuits in response to the timing signal such that the precharge circuits are activated sequentially from the one farthest from the timing control circuit to the one closest to the timing control circuit.
摘要翻译：一种半导体存储器件，其快速预充电位线并缩短访问存储器单元的周期时间。半导体存储器件包括具有多个存储单元的存储单元阵列。位线连接到多个存储单元。多个预充电电路连接到位线以将位线预充电到预定电位。定时控制电路产生定时信号。预充电控制电路响应于定时信号控制预充电电路，使得预充电电路从距定时控制电路最远的一个到最靠近定时控制电路的预充电电路顺序地被激活。

88. 发明授权

US06937001B2 Circuit for generating a reference voltage having low temperature dependency 失效
标题翻译：用于产生具有低温度依赖性的参考电压的电路
公开(公告)号：US06937001B2
公开(公告)日：2005-08-30
申请号：US10492418
申请日：2003-02-26
申请人： Yoshinori Ueda
发明人： Yoshinori Ueda
IPC分类号： G11C11/413 , G05F1/56 , G05F3/30 , H01L21/822 , H01L27/04 , H03F1/30 , G05F3/16
CPC分类号： G05F3/30 , Y10S323/907
摘要： A circuit for generating a reference voltage includes a bandgap reference circuit that exhibits low temperature dependency of the output reference voltage. Since temperature dependencies of resistances thereof are appropriately controlled so that the temperature dependency of a load current flowing through divisional resistances is eliminated, it is possible to prevent the linearity of temperature dependency of the forward direction voltages of diodes from degrading. Accordingly, the temperature dependency of output is reduced.
摘要翻译：用于产生参考电压的电路包括具有低的输出参考电压的温度依赖性的带隙基准电路。由于其电阻的温度依赖性被适当地控制，从而消除了流过分电阻的负载电流的温度依赖性，可以防止二极管的正向电压的温度依赖性的线性降低。因此，输出的温度依赖性降低。

89. 发明申请

US20050180229A1 On die termination mode transfer circuit in semiconductor memory device and its method 有权
标题翻译：半导体存储器件中芯片端接模式传输电路及其方法
公开(公告)号：US20050180229A1
公开(公告)日：2005-08-18
申请号：US10879650
申请日：2004-06-28
申请人： Seung-Eon Jin
发明人： Seung-Eon Jin
IPC分类号： H03K19/0175 , G11C7/00 , G11C7/10 , G11C11/40 , G11C11/401 , G11C11/4063 , G11C11/407 , G11C11/413
CPC分类号： G11C7/1063 , G11C7/1051 , G11C7/1057 , G11C7/222 , G11C2207/2227
摘要： An on die termination (ODT) mode transfer circuit, for use in a semiconductor memory device, including: a delay locked loop (DLL) for receiving an external clock signal in order to generate a DLL clock signal according to a power down mode and an active-standby mode; an ODT mode signal generation means for generating an ODT mode signal in response to the DLL clock signal and a clock enable signal; and an ODT control means for generating a termination resistor (RTT) signal in response to an ODT signal and the ODT mode signal.
摘要翻译：一种用于半导体存储器件的芯片终端（ODT）模式传输电路，包括：用于接收外部时钟信号的延迟锁定环（DLL），以便根据掉电模式产生DLL时钟信号，以及主动待机模式; ODT模式信号产生装置，用于响应于DLL时钟信号和时钟使能信号产生ODT模式信号; 以及用于响应于ODT信号和ODT模式信号产生终止电阻（RTT）信号的ODT控制装置。

90. 发明申请

US20050172177A1 Semiconductor memory device for correcting errors using ECC (error correcting code) circuit 审中-公开
标题翻译：用于使用ECC（纠错码）电路校正错误的半导体存储器件
公开(公告)号：US20050172177A1
公开(公告)日：2005-08-04
申请号：US10823658
申请日：2004-04-14
申请人： Kohei Oikawa
发明人： Kohei Oikawa
IPC分类号： G11C11/41 , G06F11/00 , G06F11/10 , G11C11/413 , G11C29/00 , G11C29/04
CPC分类号： G06F11/1032
摘要： A semiconductor memory device includes a memory array having at least a first area and a second area, which stores cell data, a data input circuit located closer to the first area than the second area, to which the cell data is input, and an error correction circuit which generates parity data for error correction from the cell data input to the data input circuit. The device further includes a control circuit which stores the parity data in the first area.
摘要翻译：半导体存储器件包括存储器阵列，其具有存储单元数据的至少第一区域和第二区域，位于比输入单元数据的第二区域更靠近第一区域的数据输入电路，以及错误校正电路，从输入到数据输入电路的单元数据生成用于纠错的奇偶校验数据。该装置还包括控制电路，其将奇偶数据存储在第一区域中。

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