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1. 发明授权

US08724409B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08724409B2
公开(公告)日：2014-05-13
申请号：US12947441
申请日：2010-11-16
申请人： Kang Seol Lee , Jae Hyuk Im
发明人： Kang Seol Lee , Jae Hyuk Im
IPC分类号： G11C7/00 , G11C29/00 , G05F3/16 , G05F3/20
CPC分类号： H03K19/00384
摘要： A semiconductor integrated circuit includes an internal reference voltage generation unit configured to generate an internal reference voltage; a high voltage generation unit configured to pump an external driving voltage based on the internal reference voltage applied from the internal reference voltage generation unit, and generate a high voltage having a specified level; and a reference voltage transfer unit configured to generate a test reference voltage from a reference voltage in a package test mode to correspond to a change in a driving operation of the external driving voltage applied from outside, and monitor and force the internal reference voltage.
摘要翻译：半导体集成电路包括：内部参考电压生成单元，被配置为产生内部参考电压; 高电压产生单元，被配置为基于从内部参考电压产生单元施加的内部参考电压来泵浦外部驱动电压，并产生具有指定电平的高电压; 以及参考电压传送单元，被配置为在封装测试模式下从参考电压产生测试参考电压，以对应于从外部施加的外部驱动电压的驱动操作的变化，并监视和强制内部参考电压。

2. 发明申请

US20130234765A1 VOLTAGE GENERATION CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：半导体存储器的电压发生电路
公开(公告)号：US20130234765A1
公开(公告)日：2013-09-12
申请号：US13602270
申请日：2012-09-03
申请人： Kang Seol LEE , Jae Hyuk IM
发明人： Kang Seol LEE , Jae Hyuk IM
IPC分类号： H03L5/00
CPC分类号： G11C5/14 , G11C5/145 , G11C11/4074 , H03L5/00
摘要： A voltage generation circuit of a semiconductor memory apparatus includes a plurality of pumping units configured to provide voltages to an output node; a sensing unit configured to sense a voltage level of the output node and generate a pumping enable signal; an oscillator configured to generate an oscillator signal in response to the pumping enable signal; and a control unit configured to selectively output the oscillator signal to the plurality of pumping units in response to an active signal, a power-up signal and a mode register set signal.
摘要翻译：半导体存储装置的电压产生电路包括被配置为向输出节点提供电压的多个泵送单元; 感测单元，被配置为感测所述输出节点的电压电平并产生泵送使能信号; 配置为响应于所述泵浦使能信号产生振荡器信号的振荡器; 以及控制单元，被配置为响应于有效信号，上电信号和模式寄存器设置信号而选择性地将振荡器信号输出到多个泵浦单元。

3. 发明申请

US20120105142A1 SEMICONDUCTOR APPARATUS AND METHOD OF TRIMMING VOLTAGE 有权
标题翻译：半导体装置和电压调节方法
公开(公告)号：US20120105142A1
公开(公告)日：2012-05-03
申请号：US12966706
申请日：2010-12-13
申请人： Jae Hyuk IM
发明人： Jae Hyuk IM
IPC分类号： G05F1/10
CPC分类号： G05F1/56 , H01C17/22 , Y10T307/305
摘要： A semiconductor apparatus includes: a master chip and at least one slave chip configured to be stacked one on top of another; and a through-silicon via (TSV) configured to penetrate and electrically couple the master chip and the at least one slave chip, wherein the at least one slave chip receives a reference voltage generated from the master chip via the TSV and independently trims the reference voltage and then generates an internal voltage with the trimmed reference voltage.
摘要翻译：半导体装置包括：主芯片和至少一个从属芯片，其被配置为一个在另一个的顶部上堆叠; 和贯穿硅通孔（TSV），其被配置为穿透并电耦合所述主芯片和所述至少一个从芯片，其中所述至少一个从芯片经由所述TSV接收从所述主芯片产生的参考电压，并且独立地修整所述参考电压，然后产生具有修整的参考电压的内部电压。

4. 发明授权

US08098074B2 Monitoring circuit for semiconductor device 失效
标题翻译：半导体器件监控电路
公开(公告)号：US08098074B2
公开(公告)日：2012-01-17
申请号：US12345649
申请日：2008-12-29
申请人： Chang-Ho Do , Jae-Hyuk Im
发明人： Chang-Ho Do , Jae-Hyuk Im
IPC分类号： H01H85/30 , G01R31/02
CPC分类号： G11C29/027 , G11C17/165 , G11C17/18 , G11C29/02 , G11C29/50 , G11C29/50008
摘要： Provided is a technology for monitoring the electrical resistance of an element such as a fuse whose resistance is changed due to the electrical stress among internal circuits included in a semiconductor device. The present invention provides a monitoring circuit to monitor the change in the device specification during the device is being programmed and after the device is programmed. The present invention enables the verification of an optimized condition to let the device have a certain electrical resistance, by comparing the load voltage and the fuse voltage with the reference voltage that can sense the range of resistance variation more precisely. Also, it can guarantee device reliability since it is still possible to sense electrical resistance after the electrical stress is being given. Also, the present invention can increase the utility of the fuse by possessing an output to monitor electrical resistance sensed inside of the semiconductor.
摘要翻译：提供了一种用于监视诸如由于包含在半导体器件中的内部电路之间的电应力而导致电阻改变的熔丝的元件的电阻的技术。本发明提供了一种监视电路，用于在设备被编程期间以及在设备被编程之后监视设备规格的变化。本发明能够通过将负载电压和熔丝电压与可以更精确地感测电阻变化范围的参考电压进行比较来验证优化条件以使器件具有一定的电阻。此外，它可以保证器件的可靠性，因为仍然可以在给出电应力之后感测电阻。此外，本发明还可以通过具有输出来监测半导体内部感测的电阻来增加熔断器的效用。

5. 发明授权

US07978003B2 Internal voltage generating circuit 有权
标题翻译：内部电压发生电路
公开(公告)号：US07978003B2
公开(公告)日：2011-07-12
申请号：US12630657
申请日：2009-12-03
申请人： Kang-Seol Lee , Jae-Hyuk Im
发明人： Kang-Seol Lee , Jae-Hyuk Im
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G11C5/14
摘要： There is an internal voltage generating circuit for providing a stable high voltage by making a response time short. The internal voltage generating circuit includes a charge pump unit for generate a high voltage being higher than an external voltage in response to pumping control signals and a supply driving control signal; a pumping control signal generating unit for outputting the pumping control signals to the charge pump unit based on a driving signal; and a supply driving control unit for receiving the driving signal to generate the supply driving control signal to the charge pump unit.
摘要翻译：存在内部电压产生电路，用于通过使响应时间短而提供稳定的高电压。内部电压产生电路包括电荷泵单元，用于响应于泵送控制信号和电源驱动控制信号而产生高于外部电压的高电压; 泵送控制信号产生单元，用于基于驱动信号将泵送控制信号输出到电荷泵单元; 以及电源驱动控制单元，用于接收驱动信号以向电荷泵单元产生电源驱动控制信号。

6. 发明授权

US07839200B2 Semiconductor device and data outputting method of the same 有权
标题翻译：半导体装置及其数据输出方法
公开(公告)号：US07839200B2
公开(公告)日：2010-11-23
申请号：US12130666
申请日：2008-05-30
申请人： Jae-Hyuk Im , Kee-Teok Park
发明人： Jae-Hyuk Im , Kee-Teok Park
IPC分类号： G05F1/10
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1057 , H03K19/018521
摘要： Semiconductor device and data outputting method of the same includes an on die thermal sensor (ODTS) configured to output temperature information by detecting an internal temperature of the semiconductor device and an output driver configured to control a slew rate depending on the temperature information and output data.
摘要翻译：半导体装置及其数据输出方法包括：管芯热传感器（ODTS），其配置为通过检测半导体器件的内部温度来输出温度信息;以及输出驱动器，其被配置为根据温度信息和输出数据来控制压摆率。

7. 发明授权

US07687924B2 Multi-port memory device having serial input/output interface 有权
标题翻译：具有串行输入/输出接口的多端口存储器件
公开(公告)号：US07687924B2
公开(公告)日：2010-03-30
申请号：US11645599
申请日：2006-12-27
申请人： Jae-Hyuk Im , Chang-Ho Do
发明人： Jae-Hyuk Im , Chang-Ho Do
IPC分类号： H01L23/48 , H01L23/52 , H01L23/40
CPC分类号： H01L23/50 , G11C8/16 , H01L23/5286 , H01L2924/0002 , H01L2924/19051 , H01L2924/00
摘要： A multi-port memory device includes a first package ball out region in which a plurality of balls for a serial I/O interface part are arranged; and a second package ball out region in which a plurality of balls for a dynamic random access memory (DRAM) part are arranged.
摘要翻译：多端口存储器件包括：第一封装球出区域，其中布置有用于串行I / O接口部件的多个球; 以及布置有用于动态随机存取存储器（DRAM）部分的多个球的第二包装球出口区域。

8. 发明申请

US20100027364A1 MULTI-PORT MEMORY DEVICE HAVING SELF-REFRESH MODE 有权
标题翻译：具有自激模式的多端口存储器件
公开(公告)号：US20100027364A1
公开(公告)日：2010-02-04
申请号：US12578513
申请日：2009-10-13
申请人： Jae-Hyuk Im , Chang-Ho DO
发明人： Jae-Hyuk Im , Chang-Ho DO
IPC分类号： G11C7/00 , G11C8/16 , G11C8/00
CPC分类号： G11C11/406 , G11C7/1075 , G11C8/16 , G11C11/401 , G11C11/40611 , G11C11/40615 , G11C29/50 , G11C29/50016 , G11C2207/105 , G11C2211/4065
摘要： The multi-port memory device includes a mode input/output controller for receiving a flag signal and generating a self-refresh entry signal and a self-refresh escape signal, a refresh interval signal generator for providing a self-refresh interval signal notifying a self-refresh interval in response to the self-refresh entry signal and the self-refresh escape signal, a refresh cycle signal generator for periodically generating a cycle-pulse signal during an activation of the self-refresh interval signal, an internal refresh signal generator for producing an internal refresh signal in response to the self-refresh entry signal and the cycle-pulse signal, and an internal address counter for generating an internal address in response to the internal refresh signal.
摘要翻译：多端口存储装置包括用于接收标志信号并产生自刷新入口信号和自刷新逸出信号的模式输入/输出控制器，用于提供通知自身的自刷新间隔信号的刷新间隔信号发生器 - 响应于自刷新入口信号和自刷新逸出信号的刷新间隔;刷新周期信号发生器，用于在激活自刷新间隔信号期间周期性地产生周期脉冲信号;内部刷新信号发生器，用于响应于自刷新入口信号和周期脉冲信号产生内部刷新信号，以及内部地址计数器，用于响应于内部刷新信号产生内部地址。

9. 发明申请

US20080304341A1 REDUNDANCY CIRCUIT 失效
标题翻译：冗余电路
公开(公告)号：US20080304341A1
公开(公告)日：2008-12-11
申请号：US11958320
申请日：2007-12-17
申请人： Jae Hyuk Im , Yong Ju Chon
发明人： Jae Hyuk Im , Yong Ju Chon
IPC分类号： G11C7/00
CPC分类号： G11C29/785 , G11C2229/763 , G11C2229/766
摘要： A redundancy circuit can include a first fuse set that is configured to receive an address signal and an initializing signal activated when power is up, and to output a first redundancy signal, the first redundancy signal being used to repair a defective cell by using a laser beam radiating method, a second fuse set that is configured to receive the initializing signal, a specific address signal, a test mode signal that is activated when a defective cell exists, and the address signal, and to output a second redundancy signal, the second redundancy signal being used to repair the defective cell by using an electrical fusing method, a first memory cell array that is controlled by the first redundancy signal, and a second memory cell array that is controlled by the second redundancy signal.
摘要翻译：冗余电路可以包括：第一熔丝组，其被配置为接收地址信号;以及在上电时激活的初始化信号;以及输出第一冗余信号，所述第一冗余信号用于通过使用激光器来修复有缺陷的单元波束辐射方法，被配置为接收初始化信号的第二熔丝组，特定地址信号，当存在缺陷单元时被激活的测试模式信号和地址信号，并输出第二冗余信号，第二熔丝组冗余信号用于通过使用电熔接方法修复故障单元，由第一冗余信号控制的第一存储单元阵列和由第二冗余信号控制的第二存储单元阵列。

10. 发明申请

US20080159039A1 Semiconductor memory device with refresh signal generator and its driving method 有权
标题翻译：具有刷新信号发生器的半导体存储器件及其驱动方法
公开(公告)号：US20080159039A1
公开(公告)日：2008-07-03
申请号：US11824429
申请日：2007-06-29
申请人： Jae-Hyuk Im , Chang-Ho Do
发明人： Jae-Hyuk Im , Chang-Ho Do
IPC分类号： G11C7/00 , G11C5/14 , G11C8/00
CPC分类号： G11C11/406 , G11C5/147 , G11C11/40615
摘要： A semiconductor memory device includes a level feedback circuit and a refresh signal generator. The level feedback circuit outputs a bulk voltage applied to a cell transistor as a feedback signal. The refresh signal generator generates an internal refresh signal for driving a refresh operation at predetermined intervals during a self refresh mode. A period of the internal refresh signal is adjusted according to a voltage level of the feedback signal.
摘要翻译：半导体存储器件包括电平反馈电路和刷新信号发生器。电平反馈电路输出施加到单元晶体管的体电压作为反馈信号。刷新信号发生器产生用于在自刷新模式期间以预定间隔驱动刷新操作的内部刷新信号。内部刷新信号的周期根据反馈信号的电压电平进行调整。

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