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81. 发明授权

US10804263B2 Switching field plate power MOSFET 有权
公开(公告)号：US10804263B2
公开(公告)日：2020-10-13
申请号：US15274402
申请日：2016-09-23
申请人： Texas Instruments Incorporated
发明人： Haian Lin , Frank Baiocchi
IPC分类号： H01L27/088 , H01L29/40 , H01L29/10 , H01L21/8236 , H01L29/78 , H01L29/417 , H01L21/265 , H01L29/06
摘要： A power MOSFET IC device including a source-down enhancement mode transistor formed in a semiconductor substrate and a depletion mode transistor formed in a doped region of the semiconductor substrate. A gate terminal of the depletion mode transistor is formed over at least a portion of the doped region as a field plate that is switchably connectable to a source terminal of the source-down enhancement mode transistor. A control circuit may be provided to facilitate a connection between the gate terminal of the depletion mode transistor and the source terminal of the source-down enhancement mode transistor when the power MOSFET integrated circuit is in an OFF state. The control circuit may also be configured to facilitate connection of the gate terminal of the depletion mode transistor to a gate terminal of the source-down enhancement mode FET device or to an external driver that provides a reference voltage, when the power MOSFET is in an ON state.

82. 发明授权

US10756084B2 Group-III nitride semiconductor device and method for fabricating the same 有权
公开(公告)号：US10756084B2
公开(公告)日：2020-08-25
申请号：US15612292
申请日：2017-06-02
申请人： Wen-Jang Jiang
发明人： Wen-Jang Jiang
IPC分类号： H01L29/778 , H01L29/872 , H01L21/8236 , H01L27/06 , H01L29/20 , H01L23/31 , H01L23/29 , H01L29/66 , H01L27/088 , H01L21/8252 , H01L27/02 , H01L29/205 , H01L29/868 , H01L29/51 , H01L29/207
摘要： The present invention discloses a group-III nitride semiconductor device, which comprises a substrate, a buffer layer, a semiconductor stack structure, and a passivation film. The buffer layer is disposed on the substrate. The semiconductor stack structure is disposed on the buffer layer and comprises a gate, a source, and a drain. In addition, a gate insulating layer is disposed between the gate and the semiconductor stack structure for forming a HEMT. The passivation film covers the HEMT and includes a plurality of openings corresponding to the gate, the source, and the drain, respectively. The material of the passivation film is silicon oxynitride.

83. 发明授权

US10747081B2 Thin-film transistor, thin-film transistor substrate, and liquid crystal display device 有权
公开(公告)号：US10747081B2
公开(公告)日：2020-08-18
申请号：US16077630
申请日：2016-12-13
申请人： Mitsubishi Electric Corporation
发明人： Rii Hirano , Kazunori Inoue
IPC分类号： G02F1/1368 , G02F1/1343 , H01L21/8236 , H01L27/088 , H01L29/786 , H01L27/12 , H01L29/66
摘要： A TFT in which a channel region is formed of an oxide semiconductor is provided. Threshold voltage shift due to holes photoexcited in the vicinity of a source electrode and a drain electrode is prevented so that reliability is enhanced. A lower semiconductor layer is partially provided between an oxide semiconductor layer and a gate insulating film. The lower semiconductor layer is present in at least one of a source overlapping region where the oxide semiconductor layer overlaps a source electrode and a drain overlapping region where the oxide semiconductor layer overlaps a drain electrode. In contrast, a region where the lower semiconductor layer is absent is provided between the source overlapping region and the drain overlapping region.

84. 发明授权

US10141395B2 High-K metal-insulator-metal capacitor and method of manufacturing the same 有权
公开(公告)号：US10141395B2
公开(公告)日：2018-11-27
申请号：US15832898
申请日：2017-12-06
申请人： International Business Machines Corporation
发明人： Chih-Chao Yang
IPC分类号： H01L29/00 , H01L21/8236 , H01L21/8242 , H01L21/20 , H01L49/02 , H01L21/768
摘要： A metal-insulator-metal (MIM) capacitor, includes a cross-sectional view: a first metal plate; a second metal plate; a third metal plate; and a layer of high-k material contacting the first metal plate, the second metal plate, and the third metal plate.

85. 发明授权

US09966391B2 Backplane for display apparatus 有权
公开(公告)号：US09966391B2
公开(公告)日：2018-05-08
申请号：US15263648
申请日：2016-09-13
申请人： Samsung Display Co., Ltd.
发明人： Minhyun Jin , Hyunduck Cho
IPC分类号： H01L27/108 , H01L21/8236 , H01L27/12 , H01L29/786 , H01L27/32
CPC分类号： H01L27/1255 , H01L27/1251 , H01L27/1259 , H01L27/127 , H01L27/1288 , H01L27/3262 , H01L27/3265 , H01L29/78606 , H01L29/78618 , H01L29/78621 , H01L29/78696 , H01L2227/323
摘要： A backplane for a display apparatus includes a substrate including a display area and a non-display area; a first transistor formed on the display area; and a second transistor formed on the non-display area, wherein a first active layer includes a first channel area, a first source area disposed on one side of the first channel area, a first drain area disposed on the other side of the first channel area, and a low-density doped area and a halo doped area that are adjacent to both ends of the first gate electrode, and the second active layer includes a second channel area, a second source area disposed on one side of the second channel area, and a second drain area disposed on the other side of the second channel area.

86. 发明授权

US09865599B2 Transistor with deep Nwell implanted through the gate 有权
公开(公告)号：US09865599B2
公开(公告)日：2018-01-09
申请号：US14614733
申请日：2015-02-05
申请人： Texas Instruments Incorporated
发明人： Mahalingam Nandakumar
IPC分类号： H01L29/76 , H01L29/94 , H01L21/8236 , H01L29/78 , H01L21/336 , H01L29/778 , H01L27/092 , H01L21/8238
CPC分类号： H01L27/0928 , H01L21/823814 , H01L21/823892
摘要： A method of fabricating a CMOS integrated circuit (IC) includes implanting a first n-type dopant at a first masking level that exposes a p-region of a substrate surface having a first gate stack thereon to form NLDD regions for forming n-source/drain extension regions for at least a portion of a plurality of n-channel MOS (NMOS) transistors on the IC. A p-type dopant is implanted at a second masking level that exposes an n-region in the substrate surface having a second gate stack thereon to form PLDD regions for at least a portion of a plurality of p-channel MOS (PMOS) transistors on the IC. A second n-type dopant is retrograde implanted including through the first gate stack to form a deep nwell (DNwell) for the portion of NMOS transistors. A depth of the DNwell is shallower below the first gate stack as compared to under the NLDD regions.

87. 发明申请

US20170092776A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：US20170092776A1
公开(公告)日：2017-03-30
申请号：US15372493
申请日：2016-12-08
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Shunpei YAMAZAKI , Jun KOYAMA , Hiroyuki MIYAKE , Kei TAKAHASHI , Kouhei TOYOTAKA , Masashi TSUBUKU , Kosei NODA , Hideaki KUWABARA
IPC分类号： H01L29/786 , H01L29/24 , G06K19/077 , H01L29/66 , H01L21/8236 , H01L23/66 , H01L27/088
CPC分类号： H01L29/26 , G06K19/07758 , G11C7/00 , G11C19/28 , H01L21/8236 , H01L23/66 , H01L27/0883 , H01L27/1225 , H01L29/24 , H01L29/66969 , H01L29/78609 , H01L29/7869 , H01L29/78696 , H01L2223/6677 , H02M3/07
摘要： An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel fog nation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

88. 发明授权

US09520467B1 Field effect transistor structure and manufacturing method thereof 有权
标题翻译：场效应晶体管结构及其制造方法
公开(公告)号：US09520467B1
公开(公告)日：2016-12-13
申请号：US14840752
申请日：2015-08-31
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Fu-Yu Chu , Chih-Chang Cheng , Ruey-Hsin Liu
IPC分类号： H01L21/338 , H01L21/8236 , H01L21/02 , H01L29/10 , H01L27/088 , H01L29/78 , H01L29/66
CPC分类号： H01L29/7833 , H01L21/26586 , H01L21/823412 , H01L21/823437 , H01L27/088 , H01L29/1045 , H01L29/1083 , H01L29/78
摘要： The present disclosure provides an FET structure including a substrate of a first conductive type having a top surface, a first gate over the top surface, a source and a drain of a second conductive type in the substrate, and a first channel under the first gate. A dopant concentration of a first conductive type includes double Gaussian peaks measured less than 200 nm beneath the top surface, from one end of the first gate to the other end of the first gate along the first channel. In some embodiments, the FET structure further including a second gate over the top surface and a second channel under the second gate. A dopant concentration of a first conductive type includes a single Gaussian peak measured less than 200 nm beneath the top surface, from one end of the second gate to the other end of the second gate along the second channel.
摘要翻译：本公开提供一种FET结构，其包括具有顶表面的第一导电类型的衬底，顶表面上的第一栅极，衬底中的第二导电类型的源极和漏极，以及在第一栅极下方的第一沟道。第一导电类型的掺杂剂浓度包括在顶表面下方测量的低于200nm的双高斯峰，从第一栅极的一端到第一栅极的另一端沿着第一沟道。在一些实施例中，FET结构还包括顶表面上的第二栅极和位于第二栅极下方的第二沟道。第一导电类型的掺杂剂浓度包括在顶表面下方测量的小于200nm的单个高斯峰，从第二栅极的一端到第二栅极的另一端沿着第二沟道。

89. 发明授权

US09455335B2 Techniques for ion implantation of non-planar field effect transistors 有权
标题翻译：非平面场效应晶体管离子注入技术
公开(公告)号：US09455335B2
公开(公告)日：2016-09-27
申请号：US14080461
申请日：2013-11-14
申请人： Varian Semiconductor Equipment Associates, Inc.
发明人： Anthony Renau , Hans-Joachim L. Gossmann
IPC分类号： H01L21/8236 , H01L29/66
CPC分类号： H01L29/6681 , H01L29/66537 , H01L29/66545 , H01L29/66795
摘要： A method of forming a fin field effect transistor (finFET) device includes forming a fin structure on a substrate, the substrate comprising a semiconductor material and forming a replacement gate cavity comprising an exposed portion of the fin structure and a sidewall portion adjacent the exposed portion, wherein the exposed portion of the fin structure defines a channel region. The method further includes performing at least one implant into the exposed portion of the fin structure.
摘要翻译：形成鳍状场效应晶体管（finFET）器件的方法包括在衬底上形成翅片结构，所述衬底包括半导体材料，并形成包括鳍结构的暴露部分和邻近暴露部分的侧壁部分的替换栅极腔，其中所述鳍结构的所述暴露部分限定沟道区域。该方法还包括将至少一个植入物执行到翅片结构的暴露部分中。

90. 发明申请

US20160233216A1 SEMICONDUCTOR DEVICE AND PREPARATION METHOD THEREFOR 审中-公开
标题翻译：半导体器件及其制备方法
公开(公告)号：US20160233216A1
公开(公告)日：2016-08-11
申请号：US15023049
申请日：2014-12-03
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Guangsheng ZHANG , Sen ZHANG
IPC分类号： H01L27/088 , H01L21/8236
摘要： A semiconductor device includes a substrate (110); a buried layer (120) formed on the substrate (110), a diffusion layer (130) formed on the buried layer (120), wherein the diffusion layer (130) includes a first diffusion region (132) and a second diffusion region (134), and an impurity type of the second diffusion region (134) is opposite to an impurity type of the first diffusion region (132); the diffusion layer (134) further comprises a plurality of third diffusion regions (136) formed in the second diffusion region, wherein an impurity type of the third diffusion region (136) is opposite to the impurity type of the second diffusion region (134); and a gate (144) formed on the diffusion layer (130).
摘要翻译：半导体器件包括衬底（110）; 形成在所述衬底（110）上的掩埋层（120），形成在所述掩埋层（120）上的扩散层（130），其中所述扩散层（130）包括第一扩散区域（132）和第二扩散区域 134），并且所述第二扩散区（134）的杂质类型与所述第一扩散区（132）的杂质类型相反; 扩散层（134）还包括形成在第二扩散区域中的多个第三扩散区域（136），其中第三扩散区域（136）的杂质类型与第二扩散区域（134）的杂质类型相反， ; 和形成在扩散层（130）上的栅极（144）。

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