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81. 发明申请

US20120228688A1 MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20120228688A1
公开(公告)日：2012-09-13
申请号：US13410610
申请日：2012-03-02
申请人： Daisuke MATSUBAYASHI
发明人： Daisuke MATSUBAYASHI
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/1085 , C23C14/08 , H01L21/84 , H01L27/0688 , H01L27/105 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L27/10894 , H01L27/10897 , H01L27/115 , H01L27/11507 , H01L27/11514 , H01L27/1156 , H01L27/1203 , H01L27/1207 , H01L27/1225 , H01L27/1255 , H01L28/40 , H01L29/78642 , H01L29/7869
摘要： A memory device that is as small in area as possible and has an extremely long data retention period. A transistor with extremely low leakage current is used as a cell transistor of a memory element in a memory device. Moreover, in order to reduce the area of a memory cell, the transistor is formed so that its source and drain are stacked in the vertical direction in a region where a bit line and a word line intersect each other. Further, a capacitor is stacked above the transistor.
摘要翻译：一种存储器件，其面积尽可能小，数据保存期极长。具有极低泄漏电流的晶体管被用作存储器件中的存储元件的单元晶体管。此外，为了减小存储单元的面积，晶体管形成为使得其源极和漏极在位线和字线相交的区域中沿垂直方向堆叠。此外，电容器堆叠在晶体管的上方。

82. 发明授权

US08255858B2 Method for adjusting capacitance of capacitors without affecting die area 有权
标题翻译：调整电容器电容而不影响芯片面积的方法
公开(公告)号：US08255858B2
公开(公告)日：2012-08-28
申请号：US12315122
申请日：2008-11-26
申请人： Peter Huang , Ming-Chun Chen
发明人： Peter Huang , Ming-Chun Chen
IPC分类号： G06F17/50 , H01L21/20 , H01L27/108 , H01L29/12 , H01L29/786 , H01L29/94 , H01L21/338 , H01L21/337 , H01L21/8242
CPC分类号： H01G4/33 , H01L22/14 , H01L22/20 , H01L27/0207 , H01L27/118 , H01L28/86
摘要： According to one exemplary embodiment, a method for adjusting geometry of a capacitor includes fabricating a first composite capacitor residing in a first standard cell with a first set of process parameters. The method further includes using a second standard cell having substantially same dimensions as the first standard cell. The method further includes using a capacitance value from the first composite capacitor to adjust a geometry of a second composite capacitor residing in the second standard cell, wherein the second composite capacitor is fabricated with a second set of process parameters. The geometry of the second composite capacitor can be adjusted to cause the second composite capacitor to have a capacitance value substantially equal to the capacitance value from the first composite capacitor.
摘要翻译：根据一个示例性实施例，一种用于调整电容器几何形状的方法包括制造驻留在具有第一组工艺参数的第一标准单元中的第一复合电容器。该方法还包括使用具有与第一标准单元基本相同的尺寸的第二标准单元。该方法还包括使用来自第一复合电容器的电容值来调整驻留在第二标准单元中的第二复合电容器的几何形状，其中第二复合电容器由第二组工艺参数制成。可以调整第二复合电容器的几何形状，使得第二复合电容器的电容值基本上等于来自第一复合电容器的电容值。

83. 发明授权

US08252641B2 Memory embedded logic semiconductor device having memory region and logic circuit region 有权
标题翻译：具有存储区和逻辑电路区的存储器嵌入式逻辑半导体器件
公开(公告)号：US08252641B2
公开(公告)日：2012-08-28
申请号：US12836166
申请日：2010-07-14
申请人： Yasuyuki Aoki
发明人： Yasuyuki Aoki
IPC分类号： H01L21/8238 , H01L21/8242
CPC分类号： H01L27/10894 , H01L27/105 , H01L27/10814 , H01L27/10897
摘要： In a method of manufacturing a semiconductor device, first contact holes reaching diffusion regions of a cell transistor, bit line contact holes reaching diffusion regions of the cell transistor, and interconnect grooves communicating with the bit line contact holes are buried in a first insulating film. In addition, first contact plugs and bit line contacts are respectively formed by burying conductive materials in the first contact holes, the bit line contact holes and the interconnect grooves, and the first contact plugs are electrically connected to a capacitor formed in a third insulating film through an opening formed in a second insulating film.
摘要翻译：在制造半导体器件的方法中，到达单元晶体管的扩散区域的第一接触孔，到达单元晶体管的扩散区域的位线接触孔和与位线接触孔连通的互连槽被埋在第一绝缘膜中。此外，第一接触插塞和位线触点分别通过在第一接触孔，位线接触孔和互连槽中埋入导电材料而形成，并且第一接触插塞电连接到形成在第三绝缘膜中的电容器通过形成在第二绝缘膜中的开口。

84. 发明授权

US08241981B1 Method of fabricating a deep trench (DT) metal-insulator-metal (MIM) capacitor 失效
标题翻译：制造深沟槽（DT）金属 - 绝缘体 - 金属（MIM）电容器的方法
公开(公告)号：US08241981B1
公开(公告)日：2012-08-14
申请号：US13017108
申请日：2011-01-31
申请人： Rishikesh Krishnan , Joseph F. Shepard, Jr. , Michael P. Chudzik , Christian Lavoie , Dong-Ick Lee , Oh-Jung Kwon , Unoh Kwon , Youngjin Choi
发明人： Rishikesh Krishnan , Joseph F. Shepard, Jr. , Michael P. Chudzik , Christian Lavoie , Dong-Ick Lee , Oh-Jung Kwon , Unoh Kwon , Youngjin Choi
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L27/10829 , H01L27/1087 , H01L28/40 , H01L29/66181
摘要： A method includes providing an SOI substrate including a layer of silicon disposed atop a layer of an oxide, the layer of an oxide being disposed atop the semiconductor substrate; forming a deep trench having a sidewall extending through the layer of silicon and the layer of an oxide and into the substrate; depositing a continuous spacer on the sidewall to cover the layer of silicon, the layer of an oxide and a part of the substrate; depositing a first conformal layer of a conductive material throughout the inside of the deep trench; creating a silicide within the deep trench in regions extending through the sidewall into an uncovered part of the substrate; removing the first conformal layer from the continuous spacer; removing the continuous spacer; depositing a layer of a high k dielectric material throughout the inside of the deep trench, and depositing a second conformal layer of a conductive material onto the layer of a high-k dielectric material.
摘要翻译：一种方法包括提供包括设置在氧化物层顶上的硅层的SOI衬底，所述氧化物层设置在所述半导体衬底的顶部; 形成具有延伸穿过所述硅层和所述氧化物层的侧壁并进入所述衬底的深沟槽; 在所述侧壁上沉积连续间隔物以覆盖所述硅层，所述氧化物层和所述衬底的一部分; 在深沟槽的整个内部沉积导电材料的第一共形层; 在穿过侧壁延伸到衬底的未覆盖部分的区域中的深沟槽内产生硅化物; 从所述连续间隔件中去除所述第一共形层; 去除连续间隔物; 在深沟槽的整个内部沉积高k介电材料层，以及将高导电材料的第二保形层沉积到高k电介质材料的层上。

85. 发明授权

US08222104B2 Three dimensional integrated deep trench decoupling capacitors 有权
标题翻译：三维集成深沟槽去耦电容器
公开(公告)号：US08222104B2
公开(公告)日：2012-07-17
申请号：US12509780
申请日：2009-07-27
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/8242
CPC分类号： H01L29/945 , H01L23/481 , H01L23/5223 , H01L27/0805 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit device includes forming a plurality of deep trench decoupling capacitors on a first substrate; forming a plurality of active circuit devices on a second substrate; bonding the second substrate to the first substrate; and forming electrical connections between the deep trench capacitors and the second substrate.
摘要翻译：形成集成电路器件的方法包括在第一衬底上形成多个深沟槽去耦电容器; 在第二基板上形成多个有源电路器件; 将所述第二基板接合到所述第一基板; 以及在所述深沟槽电容器和所述第二衬底之间形成电连接。

86. 发明授权

US08216897B2 Method for manufacturing a capacitor of a semiconductor device 有权
标题翻译：半导体装置的电容器的制造方法
公开(公告)号：US08216897B2
公开(公告)日：2012-07-10
申请号：US12981204
申请日：2010-12-29
申请人： Do Hyung Kim
发明人： Do Hyung Kim
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/20
CPC分类号： H01L27/10855 , H01L21/76897 , H01L27/10876 , H01L27/10894
摘要： A method for manufacturing a semiconductor device is disclosed. A method for manufacturing a semiconductor device includes forming a device isolation structure for defining an active region, forming a buried word line traversing the active region, forming one or more insulation film patterns over the buried word line, forming a line pattern including a first conductive material at a position between the insulation film patterns, and forming a plurality of storage node contacts (SNCs) by isolating the line pattern. As a result, when forming a bit line contact and a storage node contact, a fabrication margin is increased.
摘要翻译：公开了一种制造半导体器件的方法。一种制造半导体器件的方法包括形成用于限定有源区的器件隔离结构，形成穿过有源区的掩埋字线，在掩埋字线上形成一个或多个绝缘膜图案，形成包括第一导电在绝缘膜图案之间的位置处的材料，以及通过隔离线图案形成多个存储节点触点（SNC）。结果，当形成位线接触和存储节点接触时，制造裕度增加。

87. 发明申请

US20120171827A1 STRUCTURE AND METHOD TO FORM EDRAM ON SOI SUBSTRATE 有权
标题翻译：在SOI衬底上形成EDRAM的结构和方法
公开(公告)号：US20120171827A1
公开(公告)日：2012-07-05
申请号：US13417900
申请日：2012-03-12
申请人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
发明人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L29/945
摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
摘要翻译：提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和内电极以及位于沟槽电容器上方的半导体器件。半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

88. 发明授权

US08211763B2 Methods of forming vertical field effect transistors, vertical field effect transistors, and DRAM cells 有权
标题翻译：形成垂直场效应晶体管，垂直场效应晶体管和DRAM单元的方法
公开(公告)号：US08211763B2
公开(公告)日：2012-07-03
申请号：US13036725
申请日：2011-02-28
申请人： Larson D. Lindholm , David K. Hwang
发明人： Larson D. Lindholm , David K. Hwang
IPC分类号： H01L27/108 , H01L21/8242 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66666 , H01L27/0207 , H01L27/10876 , H01L29/0657 , H01L29/0692 , H01L29/7827
摘要： A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking material. A semiconductive material pillar is epitaxially grown to within the opening adjacent the masking material from the semiconductor material at the opening base. At least some of the masking material is removed from the opening. A gate dielectric is formed radially about the pillar. Conductive gate material is formed radially about the gate dielectric. An upper portion of the pillar is formed to comprise one source/drain region of the vertical transistor. Semiconductive material of the pillar received below the upper portion is formed to comprise a channel region of the vertical transistor. Semiconductor material adjacent the opening is formed to comprise another source/drain region of the vertical transistor. Other aspects and implementations are contemplated.
摘要翻译：形成垂直场效应晶体管的方法包括将开口蚀刻成半导体材料。开口底座的侧壁和径向最外部的部分衬有掩模材料。半导体材料柱外延生长在与开口底部的半导体材料的掩模材料相邻的开口内。至少一些掩模材料从开口去除。栅极电介质围绕柱径向地形成。导电栅极材料围绕栅极电介质径向地形成。柱的上部形成为包括垂直晶体管的一个源极/漏极区域。接收在上部下方的柱的半导体材料形成为包括垂直晶体管的沟道区。与开口相邻的半导体材料形成为包括垂直晶体管的另一个源极/漏极区域。考虑了其他方面和实现。

89. 发明授权

US08178404B2 Metal-insulator-metal (MIM) capacitor structure and methods of fabricating same 有权
标题翻译：金属绝缘体金属（MIM）电容器结构及其制造方法
公开(公告)号：US08178404B2
公开(公告)日：2012-05-15
申请号：US12257582
申请日：2008-10-24
申请人： Michael Olewine , Kevin Saiz
发明人： Michael Olewine , Kevin Saiz
IPC分类号： H01L21/8242
CPC分类号： H01L28/60 , H01L21/76834 , H01L21/76852 , H01L23/5223 , H01L27/016 , H01L2924/0002 , H01L2924/00
摘要： A Metal-Insulator-Metal (MIM) capacitor structure and method of fabricating the same in an integrated circuit improve capacitance density in a MIM capacitor structure by utilizing a sidewall spacer extending along a channel defined between a pair of legs that define portions of the MIM capacitor structure. Each of the legs includes top and bottom electrodes and an insulator layer interposed therebetween, as well as a sidewall that faces the channel. The sidewall spacer incorporates a conductive layer and an insulator layer interposed between the conductive layer and the sidewall of one of the legs, and the conductive layer of the sidewall spacer is physically separated from the top electrode of the MIM capacitor structure. In addition, the bottom electrode of a MIM capacitor structure may be ammonia plasma treated prior to deposition of an insulator layer thereover to reduce oxidation of the electrode. Furthermore, a multi-rate etching process may be used to etch the top electrode and insulator layer of an MIM structure, using a first, higher rate to perform an anisotropic etch up to a point proximate an interface between the conductive and dielectric materials respectively defining the top electrode and insulator layer of the MIM structure, and then using a second, lower rate to perform an anisotropic etch to a point proximate an etch stop layer defined on the bottom electrode of the MIM structure.
摘要翻译：金属 - 绝缘体 - 金属（MIM）电容器结构及其在集成电路中的制造方法通过利用沿着限定MIM部分的一对支腿之间限定的沟道延伸的侧壁间隔来改善MIM电容器结构中的电容密度电容器结构。每个腿包括顶部和底部电极以及插入其间的绝缘体层以及面向通道的侧壁。侧壁间隔物包括导电层和介于导电层和一个腿部的侧壁之间的绝缘体层，并且侧壁间隔物的导电层在物理上与MIM电容器结构的顶部电极分离。此外，MIM电容器结构的底部电极可以在其上沉积绝缘体层之前进行氨等离子体处理，以减少电极的氧化。此外，可以使用多速率蚀刻工艺来蚀刻MIM结构的顶部电极和绝缘体层，使用第一较高的速率来执行各向异性蚀刻直到接近导电和介电材料之间的界面，分别限定 MIM结构的顶部电极和绝缘体层，然后使用第二较低的速率对限定在MIM结构的底部电极上的蚀刻停止层附近的点进行各向异性蚀刻。

90. 发明授权

US08138039B2 Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array 有权
标题翻译：用于高密度，低电压逻辑和存储器阵列的垂直环绕栅极场效应晶体管
公开(公告)号：US08138039B2
公开(公告)日：2012-03-20
申请号：US13071628
申请日：2011-03-25
申请人： Sanh D. Tang , Robert J. Burke , Anand Srinivasan
发明人： Sanh D. Tang , Robert J. Burke , Anand Srinivasan
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L27/10885 , H01L27/10814 , H01L27/10876 , H01L27/10891 , H01L27/1203 , H01L29/42392 , H01L29/78642
摘要： A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.
摘要翻译：具有环绕栅极的垂直晶体管和制造这种晶体管的方法。环绕栅极（WAG）垂直晶体管通过其中晶体管的源极，漏极和沟道区域通过制造工艺自动限定和对准而不进行光刻图案化的工艺制造。

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