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81. 发明申请

US20130140668A1 Forming Structures on Resistive Substrates 有权
标题翻译：电阻基板上的形成结构
公开(公告)号：US20130140668A1
公开(公告)日：2013-06-06
申请号：US13312442
申请日：2011-12-06
申请人： Alan B. Botula , Renata Camillo-Castillo , James S. Dunn , Jeffrey P. Gambino , Douglas B. Hershberger , Alvin J. Joseph , Mark E. Stidham , Robert M. Rassel
发明人： Alan B. Botula , Renata Camillo-Castillo , James S. Dunn , Jeffrey P. Gambino , Douglas B. Hershberger , Alvin J. Joseph , Mark E. Stidham , Robert M. Rassel
IPC分类号： H01L27/04 , H01L21/76
CPC分类号： H01L21/76224 , H01L21/26506 , H01L21/823892 , H01L27/04 , H01L27/0623 , H01L27/0635 , H01L27/0802 , H01L27/0811 , H01L27/0928
摘要： A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.
摘要翻译：衬底包括具有第一电阻率的第一区域，用于优化场效应晶体管，具有第二电阻率的第二区域，用于优化双极晶体管器件和三阱的npn子集电极，具有第三电阻率的第三区域，具有第三电阻率用于无源器件的高电阻率，第四区域，基本上没有植入，以为器件提供低周边电容。

82. 发明申请

US20130105938A1 DEVICE MATCHING LAYOUT AND METHOD FOR IC 有权
标题翻译： IC的设备匹配布局和方法
公开(公告)号：US20130105938A1
公开(公告)日：2013-05-02
申请号：US13633267
申请日：2012-10-02
申请人： Silergy Semiconductor Technology (Hangzhou)
发明人： Shuai Cheng
IPC分类号： G06F17/50 , H01L27/04
CPC分类号： H01L27/0802 , G06F17/5045 , H01L27/0207
摘要： The present invention relates to device matching in an integrated circuit. In one embodiment, an integrated circuit of matched devices can include: N main-devices to be matched by 4×K sub-devices configured to form K device arrays, where each of the device arrays includes four sub-device groups arrayed symmetrically around a vertical axis and a horizontal axis, where each of the sub-device groups includes N sub-devices arrayed with equal distance along a direction of the vertical axis, where K and N are integers, and N is larger than two; metal lead wires arrayed in parallel and with equal distance, and configured to connect the main-devices; a common connecting wire configured to connect common nodes of the sub-devices together; and where four sub-devices arrayed in the four sub-device groups, and other sub-devices arrayed in other sub-device groups, are coupled to form 4×K sub-devices to match the main-devices.
摘要翻译：本发明涉及集成电路中的器件匹配。在一个实施例中，匹配设备的集成电路可以包括：被配置为形成K个设备阵列的4×K子设备匹配的N个主设备，其中每个设备阵列包括四个子设备组，垂直轴和水平轴，其中每个子装置组包括沿着垂直轴的方向排列成等距离的N个子装置，其中K和N是整数，并且N大于2; 金属引线并联排列，距离相等，并配置为连接主设备; 配置为将所述子设备的公共节点连接在一起的公共连接线; 并且其中排列在四个子设备组中的四个子设备以及排列在其他子设备组中的其他子设备被耦合以形成4×K个子设备以匹配主设备。

83. 发明申请

US20130105798A1 THIN-FILM SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THIN-FILM SEMICONDUCTOR DEVICE 有权
标题翻译：薄膜半导体器件及制造薄膜半导体器件的方法
公开(公告)号：US20130105798A1
公开(公告)日：2013-05-02
申请号：US13710969
申请日：2012-12-11
申请人： PANASONIC CORPORATION
发明人： Arinobu KANEGAE , Takahiro KAWASHIMA
IPC分类号： H01L27/04 , H01L21/77
CPC分类号： H01L27/04 , G02F1/136213 , H01L21/77 , H01L27/124 , H01L27/1255 , H01L27/1288 , H01L27/3262 , H01L29/42384 , H01L29/4908 , H01L29/78633
摘要： A thin-film semiconductor device includes a semiconductor device part and a capacitor part. The semiconductor device part includes: a light-transmitting first gate electrode; a light-shielding second gate electrode; a first insulating layer; a semiconductor layer; a second insulating layer; and a source electrode and a drain electrode. The capacitor part includes: a first capacitor electrode made of a light-transmitting conductive material; a dielectric layer; and a second capacitor electrode. The second gate electrode, the semiconductor layer, and the second insulating layer have outlines that are coincident with one another in a top view.
摘要翻译：薄膜半导体器件包括半导体器件部分和电容器部分。半导体器件部分包括：透光第一栅电极; 遮光第二栅电极; 第一绝缘层; 半导体层; 第二绝缘层; 以及源电极和漏电极。电容器部包括：由透光导电材料制成的第一电容器电极; 电介质层; 和第二电容器电极。第二栅电极，半导体层和第二绝缘层具有在俯视图中彼此重合的轮廓。

84. 发明申请

US20130099348A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：US20130099348A1
公开(公告)日：2013-04-25
申请号：US13716310
申请日：2012-12-17
申请人： Hiroyuki NAGASHIMA
发明人： Hiroyuki NAGASHIMA
IPC分类号： H01L27/04
CPC分类号： H01L27/04 , H01L27/0207 , H01L27/0688 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/10 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： A non-volatile semiconductor memory device includes: a cell array including a plurality of first wirings, a plurality of second wirings that intersects the plurality of first wirings, and memory cells that are formed at intersections of the first wirings and the second wirings and are connected between the first and second wirings; a first contact plug that comes into contact with a side portion of the first wiring provided at a first position and extends to the first wiring provided at a second position higher than the first position in a laminated direction; and a second contact plug that comes into contact with a side portion of the second wiring provided at a third position between the first position and the second position and extends to the second wiring provided at a fourth position higher than the second position in the laminated direction.
摘要翻译：非易失性半导体存储器件包括：包括多个第一布线的多个第一布线，与多个第一布线相交的多个第二布线，以及形成在第一布线和第二布线的交叉处的存储单元的单元阵列，连接在第一和第二布线之间; 第一接触插塞，其与设置在第一位置处的第一布线的侧部接触并且延伸到设置在高于第一位置的层叠方向的第二位置处的第一布线; 以及第二接触插塞，其与设置在第一位置和第二位置之间的第三位置处的第二配线的侧部接触，并且延伸到设置在高于第二位置的层叠方向上的第四位置处的第二配线。

85. 发明申请

US20130087881A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：US20130087881A1
公开(公告)日：2013-04-11
申请号：US13691071
申请日：2012-11-30
申请人： PANASONIC CORPORATION
发明人： Tomoaki IKEGAMI , Hidetoshi NISHIMURA
IPC分类号： H01L27/04
CPC分类号： H01L27/04 , H01L23/5286 , H01L27/0207 , H01L27/11807 , H01L2027/11881 , H01L2924/0002 , H01L2924/00
摘要： An interconnect plug which connects a first circuit metal interconnect to a second circuit metal interconnect provided above the first circuit metal interconnect is disposed near a feeding plug which connects a first feeding metal interconnect to a second feeding metal interconnect provided above the first feeding metal interconnect. The feeding plug and the interconnect plug are displaced relative to each other in a direction in which the first feeding metal interconnect extends.
摘要翻译：将第一电路金属互连连接到设置在第一电路金属互连上方的第二电路金属互连的互连插头设置在将第一馈电金属互连连接到设置在第一馈电金属互连之上的第二馈电金属互连的馈电插头附近。馈电插头和互连插头在第一馈电金属互连件延伸的方向上相对于彼此移位。

86. 发明申请

US20130062724A1 Power Module and Power Converter Containing Power Module 有权
标题翻译：功率模块和功率转换器包含功率模块
公开(公告)号：US20130062724A1
公开(公告)日：2013-03-14
申请号：US13638394
申请日：2011-03-30
申请人： Takeshi Tokuyama , Kinya Nakatsu , Toshiya Satoh , Hideaki Ishikawa
发明人： Takeshi Tokuyama , Kinya Nakatsu , Toshiya Satoh , Hideaki Ishikawa
IPC分类号： H01L27/04 , H01L23/48
CPC分类号： H05K7/1432 , H01L23/492 , H01L24/33 , H01L24/40 , H01L25/072 , H01L25/18 , H01L2224/291 , H01L2224/29109 , H01L2224/29111 , H01L2224/32245 , H01L2224/33 , H01L2224/40137 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48472 , H01L2224/73265 , H01L2224/83801 , H01L2224/8384 , H01L2224/84801 , H01L2224/8484 , H01L2924/01012 , H01L2924/01029 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/351 , H02M1/32 , H02M7/003 , H05K7/20927 , H01L2924/00 , H01L2924/0105 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/0103 , H01L2924/01048 , H01L2924/01049 , H01L2924/01083 , H01L2924/00014 , H01L2924/00012
摘要： A power module includes a semiconductor chip, a first coupling conductor with one main surface coupled to one main surface of the semiconductor chip, a second coupling conductor with one main surface coupled to the other main surface of the semiconductor chip, a coupling terminal supplied with electrical power from the direct current power source, and resin material to seal the semiconductor chip, and in which the resin member has a protruding section that protrudes from the space where the first and second coupling conductors are formed opposite each other, and the coupling terminal is clamped on the protruding section, and at least one of the first or second coupling conductors is coupled to a coupling terminal by way of a metallic material that melts at a specified temperature.
摘要翻译：功率模块包括半导体芯片，具有耦合到半导体芯片的一个主表面的一个主表面的第一耦合导体，具有耦合到半导体芯片的另一主表面的一个主表面的第二耦合导体，来自直流电源的电力和用于密封半导体芯片的树脂材料，并且其中树脂构件具有从第一和第二耦合导体彼此相对的空间突出的突出部分，并且耦合端子被夹紧在突出部分上，并且第一或第二耦合导体中的至少一个通过在特定温度下熔化的金属材料耦合到耦合端子。

87. 发明申请

US20130056850A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20130056850A1
公开(公告)日：2013-03-07
申请号：US13593084
申请日：2012-08-23
申请人： Ippei KUME , Kenichiro Hijioka , Naoya Inoue , Hiroyuki Kunishima , Manabu Iguchi , Hiroki Shirai
发明人： Ippei KUME , Kenichiro Hijioka , Naoya Inoue , Hiroyuki Kunishima , Manabu Iguchi , Hiroki Shirai
IPC分类号： H01L27/04 , H01L21/02
CPC分类号： H01L27/10894 , H01L27/10808 , H01L27/10814 , H01L27/10852 , H01L28/90
摘要： To provide a semiconductor device featuring reduced variation in capacitor characteristics. In the semiconductor device, a protective layer is provided at the periphery of the upper end portion of a recess (hole). This protective layer has a dielectric constant higher than that of an insulating layer placed in the same layer as the protective layer and configuring a multilayer wiring layer placed in a logic circuit region.
摘要翻译：提供具有降低的电容特性变化的半导体器件。在半导体装置中，在凹部（孔）的上端部的周围设有保护层。该保护层的介电常数高于与保护层位于同一层的绝缘层的介电常数，并且构成放置在逻辑电路区域中的多层布线层。

88. 发明申请

US20130001649A1 SEMICONDUCTOR DEVICE EMPLOYING CIRCUIT BLOCKS HAVING THE SAME CHARACTERISTICS 失效
标题翻译：使用具有相同特性的电路块的半导体器件
公开(公告)号：US20130001649A1
公开(公告)日：2013-01-03
申请号：US13517690
申请日：2012-06-14
申请人： Hiroshi SHIMIZU , Takamitsu ONDA
发明人： Hiroshi SHIMIZU , Takamitsu ONDA
IPC分类号： H01L27/04 , H01L27/088
CPC分类号： G11C11/4096 , G11C7/1096 , G11C11/4097 , H01L27/0207 , H01L27/10897
摘要： A semiconductor device is disclosed, which comprises First and second inputs ports, first and second output nodes, and first and second transistors. The first transistor includes first and second diffusion regions defining a first channel region and a first gate electrode and connected to the first input port, the first diffusion region being connected to the first output node, the second diffusion region being disposed between the first diffusion region and the first input port and supplied with a first operating potential. The second transistor includes third and fourth diffusion regions defining a second channel region and a second gate electrode and connected to the second input port, the third diffusion region being supplied with the first operating potential, the fourth diffusion region being disposed between the third diffusion region and the second input port and connected to the second output node.
摘要翻译：公开了一种半导体器件，其包括第一和第二输入端口，第一和第二输出节点以及第一和第二晶体管。第一晶体管包括限定第一沟道区和第一栅电极并连接到第一输入端的第一扩散区和第二扩散区，第一扩散区连接到第一输出节点，第二扩散区设置在第一扩散区和第一输入端口并提供第一工作电位。第二晶体管包括限定第二沟道区和第二栅极并连接到第二输入端的第三和第四扩散区，第三扩散区被提供有第一工作电位，第四扩散区设置在第三扩散区之间和第二输入端口并连接到第二输出节点。

89. 发明申请

US20120326266A1 HIGH-VOLTAGE SEMICONDUCTOR DEVICE 有权
标题翻译：高压半导体器件
公开(公告)号：US20120326266A1
公开(公告)日：2012-12-27
申请号：US13169008
申请日：2011-06-26
申请人： Shih-Chieh Pu , Ching-Ming Lee , Wei-Lun Hsu , Chih-Chung Wang , Ke-Feng Lin
发明人： Shih-Chieh Pu , Ching-Ming Lee , Wei-Lun Hsu , Chih-Chung Wang , Ke-Feng Lin
IPC分类号： H01L27/04
CPC分类号： H01L29/8611 , H01L27/0255 , H01L29/0619 , H01L29/0649 , H01L29/36
摘要： A high-voltage semiconductor device is disclosed. The HV semiconductor device includes: a substrate; a well of first conductive type disposed in the substrate; a first doping region of second conductive type disposed in the p-well; a first isolation structure disposed in the well of first conductive type and surrounding the first doping region of second conductive type; and a first drift ring of second conductive type disposed between the first doping region of second conductive type and the first isolation structure.
摘要翻译：公开了一种高压半导体器件。 HV半导体装置包括：基板; 设置在基板中的第一导电类型的阱; 布置在p阱中的第二导电类型的第一掺杂区; 第一隔离结构，设置在第一导电类型的阱中，并且包围第二导电类型的第一掺杂区; 以及设置在第二导电类型的第一掺杂区域和第一隔离结构之间的第二导电类型的第一漂移环。

90. 发明申请

US20120319230A1 ETCHING NARROW, TALL DIELECTRIC ISOLATION STRUCTURES FROM A DIELECTRIC LAYER 有权
标题翻译：蚀刻NARROW，介电层的电介质隔离结构
公开(公告)号：US20120319230A1
公开(公告)日：2012-12-20
申请号：US13164619
申请日：2011-06-20
申请人： Chia-Ying Liu , Keh-Chiang Ku , Wu-Zhang Yang
发明人： Chia-Ying Liu , Keh-Chiang Ku , Wu-Zhang Yang
IPC分类号： H01L21/762 , H01L27/04 , B82Y40/00
CPC分类号： H01L27/1463 , H01L21/76232 , H01L27/14683
摘要： Methods of forming isolation structures are disclosed. A method of forming isolation structures for an image sensor array of one aspect may include forming a dielectric layer over a semiconductor substrate. Narrow, tall dielectric isolation structures may be formed from the dielectric layer. The narrow, tall dielectric isolation structures may have a width that is no more than 0.3 micrometers and a height that is at least 1.5 micrometers. A semiconductor material may be epitaxially grown around the narrow, tall dielectric isolation structures. Other methods and apparatus are also disclosed.
摘要翻译：公开了形成隔离结构的方法。形成一个方面的图像传感器阵列的隔离结构的方法可以包括在半导体衬底上形成电介质层。可以从电介质层形成窄的高介电隔离结构。窄的高介电隔离结构可以具有不超过0.3微米的宽度和至少1.5微米的高度。半导体材料可以围绕窄的高介电隔离结构外延生长。还公开了其它方法和装置。

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