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1. 发明申请

US20190013356A1 MEMORY CELLS AND DEVICES 审中-公开
公开(公告)号：US20190013356A1
公开(公告)日：2019-01-10
申请号：US15641729
申请日：2017-07-05
申请人： Xerox Corporation
发明人： Jin Wu , Lin Ma
IPC分类号： H01L27/24 , C09D4/00 , H01L45/00
CPC分类号： H01L27/2463 , C09D4/00 , G11C11/22 , H01L45/10 , H01L45/1233 , H01L45/14 , Y10T428/105 , Y10T428/1164
摘要： Disclosed are memory cells that include a crosslinked mixture of a photoinitiator, a polyether-modified acrylate oligomer, a polyester acrylic resin, and a component selected from the group consisting of a silicone acrylate oligomer, and a fluorinated acrylate oligomer, and memory devices that contain a plurality of memory cells.

2. 发明申请

US20180254414A1 METHOD OF MANUFACTURING A MEMORY DEVICE 审中-公开
公开(公告)号：US20180254414A1
公开(公告)日：2018-09-06
申请号：US15878036
申请日：2018-01-23
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES , STMICROELECTRONICS (CROLLES 2) SAS
发明人： Sophie BERNASCONI , Christelle Charpin-Nicolle , Aomar Halimaoui
IPC分类号： H01L45/00 , G11C13/00
CPC分类号： H01L45/10 , G11C13/0007 , G11C13/0011 , G11C13/0069 , G11C2013/0078 , G11C2213/32 , G11C2213/52 , G11C2213/56 , H01L21/02258 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/1273 , H01L45/146 , H01L45/16 , H01L45/1641
摘要： The present invention relates to a memory device comprising a first electrode (27), a second electrode (28) and an active portion that can change conductive state, positioned between a first face of the first electrode (27) and a first face of the second electrode (28).The first electrode (27) comprises an upper portion forming the first face of the first electrode (27). At least one out of the upper portion and the active portion that can change conductive state comprises a porous layer (15).

3. 发明申请

US20170025605A1 RESISTIVE RANDOM ACCESS MEMORY DEVICE EMBEDDING TUNNEL INSULATING LAYER AND MEMORY ARRAY USING THE SAME AND FABRICATION METHOD THEREOF 有权
标题翻译：电阻随机访问存储器件嵌入式隧道绝缘层和使用其的存储器阵列及其制造方法
公开(公告)号：US20170025605A1
公开(公告)日：2017-01-26
申请号：US15182640
申请日：2016-06-15
申请人： Seoul National University R&DB FOUNDATION , Gachon University of Industry-Academic cooperation Foundation
发明人： Byung-Gook Park , Seongjae Cho , Sungjun Kim
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L27/2463 , G11C13/0007 , G11C13/004 , G11C2013/005 , G11C2213/15 , G11C2213/33 , G11C2213/54 , H01L27/2409 , H01L27/2472 , H01L45/10 , H01L45/1233 , H01L45/145 , H01L45/147 , H01L45/148 , H01L45/149 , H01L45/1616
摘要： A resistive random access memory device is provided with a tunneling insulator layer between a resistance change layer and a bottom electrode. Thus, it is possible: to raise the selection (on/off) ratio by the current of a direct tunneling induced by low voltage in the unselected cell and the current of an F-N tunneling induced by high voltage in the selected cell, to efficiently suppress the leakage current in the read operation, to make a low current operation less μA level by controlling the thickness of the tunneling insulator layer, and to be simultaneously fabricated together with circuit devices by forming the bottom electrodes (word lines) with a semiconductor material.
摘要翻译：电阻随机存取存储器件在电阻变化层和底部电极之间设置有隧道绝缘体层。因此，可以通过在未选择的单元中由低电压引起的直接隧道的电流和在所选择的单元中由高电压引起的FN隧穿的电流来提高选择（开/关）比，以有效地抑制在读取操作中的漏电流，通过控制隧穿绝缘体层的厚度来使低电流操作更小的μA电平，并且通过用半导体材料形成底电极（字线）与电路器件同时制造。

4. 发明申请

US20170012052A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20170012052A1
公开(公告)日：2017-01-12
申请号：US15097485
申请日：2016-04-13
申请人： Samsung Electronics Co., Ltd.
发明人： WON-CHUL JANG , Hong-soo Kim , Tae-keun Cho
IPC分类号： H01L27/115 , H01L23/522 , G11C16/04 , G11C16/08 , G11C16/26 , H01L29/788 , H01L27/24 , H01L45/00 , H01L27/22 , H01L43/08 , H01L43/10 , G11C11/16 , H01L23/528 , G11C16/10
CPC分类号： H01L27/11582 , G11C16/0483 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L27/222 , H01L27/249 , H01L29/7889 , H01L43/08 , H01L45/06 , H01L45/10 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1675
摘要： A semiconductor memory device includes string select lines extending in a first direction, vertical pillars connected to the string select lines, sub-interconnections on the string select lines, bitlines connected to the vertical pillars through the sub-interconnections, and upper contact plugs connecting the sub-interconnections to the bitlines. The string select lines include odd and even string select lines alternately arranged in a second direction. The sub-interconnections each connect a pair of vertical pillars respectively connected to one of the odd string select lines and one of the even string select lines that are adjacent to each other. Each of the upper contact plugs is between one of the sub-interconnections and one of the bitlines. Each of the upper contact plugs is arranged more adjacent to one string select line of the adjacent string select lines to which the pair of vertical pillars connected by the sub-interconnections are connected.
摘要翻译：半导体存储器件包括沿第一方向延伸的串选择线，连接到串选择线的垂直柱，串选择线上的子互连，通过子互连连接到垂直柱的位线，以及连接与位线的子互连。字符串选择行包括在第二方向交替布置的奇数和偶数字符串选择行。子互连每个连接一对垂直柱，其分别连接到奇数串选择线之一和彼此相邻的偶数串选择线之一。每个上部接触插塞位于一个子互连和一个位线之间。每个上接触插塞被布置成更靠近由相互连接的一对垂直柱连接的相邻串选择线的一个串选择线。

5. 发明授权

US09543375B2 MIM/RRAM structure with improved capacitance and reduced leakage current 有权
标题翻译： MIM / RRAM结构具有改进的电容和减小的漏电流
公开(公告)号：US09543375B2
公开(公告)日：2017-01-10
申请号：US14316910
申请日：2014-06-27
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Jian-Shiou Huang , Yao-Wen Chang , Hsing-Lien Lin , Cheng-Yuan Tsai , Chia-Shiung Tsai
IPC分类号： H01L49/02 , H01L21/02
CPC分类号： H01L28/40 , H01L21/02112 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02181 , H01L21/02266 , H01L23/5223 , H01L29/88 , H01L45/08 , H01L45/10
摘要： Some embodiments of the present disclosure provide an integrated circuit (IC) device including a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes a lower metal capacitor electrode, an upper metal capacitor electrode, and a capacitor dielectric separating the lower metal capacitor electrode from the upper metal capacitor electrode. The capacitor dielectric is made up of an amorphous oxide/nitride matrix and a plurality of metal or metal oxide/nitride nano-particles that are randomly distributed over the volume of amorphous oxide/nitride matrix.
摘要翻译：本公开的一些实施例提供了包括金属 - 绝缘体 - 金属（MIM）电容器结构的集成电路（IC）装置。 MIM电容器结构包括下金属电容器电极，上金属电容器电极和将下金属电容器电极与上金属电容器电极分离的电容器电介质。电容器电介质由无定形氧化物/氮化物基体和随机分布在无定形氧化物/氮化物基体的体积上的多个金属或金属氧化物/氮化物纳米颗粒构成。

6. 发明授权

US09281345B2 Resistance change type memory device with three-dimensional structure 有权
标题翻译：具有三维结构的电阻变化型存储器件
公开(公告)号：US09281345B2
公开(公告)日：2016-03-08
申请号：US14107442
申请日：2013-12-16
申请人： Kabushiki Kaisha Toshiba
发明人： Hiroshi Kanno , Yoichi Minemura , Takayuki Tsukamoto , Takamasa Okawa , Atsushi Yoshida , Hideyuki Tabata
IPC分类号： H01L29/02 , H01L27/24 , H01L45/00
CPC分类号： H01L27/2436 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/085 , H01L45/10 , H01L45/1226 , H01L45/14 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1616 , H01L45/1675
摘要： According to an embodiment, a non-volatile memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction orthogonal to the first direction. The device includes third wirings, and a first and a second memory. The third wirings extend in a third direction crossing the first direction and orthogonal to the second direction, and aligned in the second direction on both sides of the second wiring. The first memory is provided between one of third wiring pair and the second wiring, the pair of third wirings facing each other across the second wiring. The second memory is provided between another one of the third wiring pair and the second wiring. The second wiring has a block portion between a first portion in contact with the first memory and a second portion in contact with the second memory.
摘要翻译：根据实施例，非易失性存储器件包括沿第一方向延伸的第一布线，沿与第一方向正交的第二方向延伸的第二布线。该设备包括第三布线，以及第一和第二存储器。第三配线在与第一方向交叉的第三方向上延伸并且与第二方向垂直，并且在第二布线的两侧沿第二方向对齐。第一存储器设置在第三布线对和第二布线中的一个之间，所述一对第三布线跨越第二布线彼此面对。第二存储器设置在第三布线对和第二布线中的另一个之间。第二布线具有与第一存储器接触的第一部分和与第二存储器接触的第二部分之间的块部分。

7. 发明授权

US09252097B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09252097B2
公开(公告)日：2016-02-02
申请号：US13599153
申请日：2012-08-30
申请人： Yasuyuki Baba
发明人： Yasuyuki Baba
IPC分类号： H01L27/24 , H01L23/498 , H01L45/00 , H01L27/02
CPC分类号： H01L23/49844 , H01L27/0207 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/10 , H01L45/1233 , H01L45/141 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor memory device comprises a plurality of first wiring lines extending in a first direction, a plurality of second wiring lines extending in a second direction crossing the first direction, and a memory cell array comprising memory cells, the memory cells being connected to the first wiring lines and second wiring lines in the crossing portions of the first and second wiring lines. A plurality of first dummy-wiring-line regions are formed in the peripheral area around the memory cell array. A contact is formed in the peripheral area, the contact extending in a third direction perpendicular to the first and second directions. A plurality of second dummy-wiring-line regions are formed in the periphery of the contact. The mean value of the areas of the second dummy-wiring-line regions is less than the mean value of the areas of the first dummy-wiring-line regions.
摘要翻译：半导体存储器件包括沿第一方向延伸的多个第一布线，沿与第一方向交叉的第二方向延伸的多个第二布线，以及包括存储单元的存储单元阵列，存储单元连接到第一布线第一布线和第二布线的交叉部分中的布线和第二布线。在存储单元阵列周围的周边区域中形成多个第一虚设布线区域。接触件形成在周边区域中，接触件沿垂直于第一和第二方向的第三方向延伸。多个第二虚设布线区域形成在触点的周围。第二虚拟布线区域的面积的平均值小于第一虚拟布线区域的面积的平均值。

8. 发明申请

US20150325786A1 RRAM CELL STRUCTURE WITH LATERALLY OFFSET BEVA/TEVA 有权
标题翻译： RRAM细胞结构与侧向BEVA / TEVA
公开(公告)号：US20150325786A1
公开(公告)日：2015-11-12
申请号：US14803377
申请日：2015-07-20
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chih-Yang Chang , Wen-Ting Chu , Kuo-Chi Tu , Yu-Wen Liao , Hsia-Wei Chen , Chin-Chieh Yang , Sheng-Hung Shih , Wen-Chun You
IPC分类号： H01L45/00
CPC分类号： H01L45/124 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/10 , H01L45/12 , H01L45/1206 , H01L45/1213 , H01L45/122 , H01L45/1226 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/126 , H01L45/1266 , H01L45/1273 , H01L45/1286 , H01L45/1293 , H01L45/14 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/149 , H01L45/16 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1633 , H01L45/1641 , H01L45/165 , H01L45/1658 , H01L45/1666 , H01L45/1675 , H01L45/1683 , H01L45/1691
摘要： The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell. The method forms a bottom electrode over a bottom electrode via. The method further forms a variable resistive dielectric layer over the bottom electrode, and a top electrode over the variable resistive dielectric layer. The method forms a top electrode via vertically extending outward from an upper surface of the top electrode at a position centered along a first axis that is laterally offset from a second axis centered upon the bottom electrode via. The top electrode via has a smaller width than the top electrode. Laterally offsetting the top electrode via from the bottom electrode via provides the top electrode via with good contact resistance.
摘要翻译：本公开涉及一种形成电阻随机存取存储器（RRAM）单元的方法。该方法在底部电极通孔上形成底部电极。该方法进一步在底部电极上形成可变电阻介质层，以及在可变电阻介质层上形成顶部电极。该方法通过从顶部电极的上表面向外垂直延伸的形式形成顶部电极，所述顶部电极沿着第一轴线位于以与底部电极通孔为中心的第二轴线侧向偏移的位置。顶部电极通孔具有比顶部电极更小的宽度。顶部电极通孔从底部电极通过提供顶部电极通孔具有良好的接触电阻。

9. 发明授权

US09184383B2 Nonvolatile memory device having an electrode interface coupling region 有权
标题翻译：具有电极接口耦合区域的非易失性存储器件
公开(公告)号：US09184383B2
公开(公告)日：2015-11-10
申请号：US14156762
申请日：2014-01-16
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Yun Wang , Tony P. Chiang , Imran Hashim
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/1608 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/065 , H01L45/08 , H01L45/10 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/1616 , H01L45/1625
摘要： Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.
摘要翻译：本发明的实施例一般涉及具有设置在至少一个电极和形成在非易失性存储器件中的可变电阻层之间的界面层结构的电阻式开关非易失性存储器件及其形成方法。通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。在电阻式开关非易失性存储器件的一种结构中，界面层结构包括钝化区域，界面耦合区域和/或可变电阻层接口区域，其被配置为调整非易失性存储器件的性能，例如降低形成器件的开关电流并降低器件的成型电压，并降低从一个成形器件到另一个器件的性能变化。

10. 发明授权

US09178149B2 Surface treatment to improve resistive-switching characteristics 有权
标题翻译：表面处理提高电阻开关特性
公开(公告)号：US09178149B2
公开(公告)日：2015-11-03
申请号：US14325015
申请日：2014-07-07
申请人： Intermolecular Inc.
发明人： Michael Miller , Tony P. Chiang , Xiying Costa , Tanmay Kumar , Prashant B Phatak , April Schricker
IPC分类号： H01L21/20 , H01L45/00 , H01L21/265 , H01L21/3115 , H01L29/861 , H01L27/24
CPC分类号： H01L45/16 , H01L21/265 , H01L21/31155 , H01L27/2463 , H01L29/8615 , H01L45/08 , H01L45/10 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/165
摘要： This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.
摘要翻译：本公开提供了制造半导体器件层和相关联的存储单元结构的方法。通过进行半导体器件层的表面处理（例如离子轰击）以产生具有有意深度分布的缺陷，可以创建具有更一致的电参数的多层存储单元。例如，在电阻式开关存储单元中，可以获得设定和复位电压的更紧密的分配和较低的成形电压，从而提高器件的产量和可靠性。在至少一个实施例中，选择深度轮廓以调制缺陷的类型及其对被轰击的金属氧化物层的电性能的影响并增强均匀的缺陷分布。

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