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1. 发明申请

US20190035643A1 SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR PACKAGE DEVICE USING THE SAME 审中-公开
公开(公告)号：US20190035643A1
公开(公告)日：2019-01-31
申请号：US16136042
申请日：2018-09-19
申请人： ADVANPACK SOLUTIONS PTE LTD.
发明人： Jimmy Hwee-Seng CHEW , Kian-Hock LIM , Oviso Dominador Fortaleza, JR. , Shoa-Siong LIM
IPC分类号： H01L21/56 , H01L23/498 , H01L21/683 , H01L21/48 , H01L23/00 , H01L23/31
CPC分类号： H01L21/568 , H01L21/4846 , H01L21/486 , H01L21/6835 , H01L23/3107 , H01L23/49861 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2221/68345 , H01L2221/68381 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/85447 , H01L2924/00014 , H01L2924/181 , H01L2924/207 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015
摘要： A semiconductor structure for manufacturing a semiconductor package device is provided. The semiconductor structure includes a carrier and a dielectric layer. The carrier has a first surface and a second surface opposite to the first surface. The carrier includes an inner core layer and an exterior clad layer, and the inner core layer is covered by the exterior clad layer. The dielectric layer is formed on the first surface of the carrier. The carrier supports the dielectric layer.

2. 发明授权

US10109503B2 Method of manufacturing semiconductor package device 有权
公开(公告)号：US10109503B2
公开(公告)日：2018-10-23
申请号：US13556022
申请日：2012-07-23
申请人： Jimmy Hwee-Seng Chew , Oviso Dominador Jr Fortaleza , Kian-Hock Lim , Shoa-Siong Lim
发明人： Jimmy Hwee-Seng Chew , Oviso Dominador Jr Fortaleza , Kian-Hock Lim , Shoa-Siong Lim
IPC分类号： H01L21/00 , H01L21/56 , H01L21/683 , H01L23/498 , H01L21/48 , H01L23/31 , H01L23/00
摘要： A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a carrier. The carrier has a first surface and a second surface opposite to the first surface. The carrier includes an inner core layer and an exterior clad layer, and the inner core layer is covered by the exterior clad layer.

3. 发明申请

US20160118349A1 SEMICONDUCTOR PACKAGE 有权
标题翻译：半导体封装
公开(公告)号：US20160118349A1
公开(公告)日：2016-04-28
申请号：US14961825
申请日：2015-12-07
申请人： ADVANPACK SOLUTIONS PTE LTD.
发明人： Hwee-Seng Jimmy CHEW , Kian-Hock LIM , Oviso Dominador Jr FORTALEZA , Shoa-Siong Raymond LIM
IPC分类号： H01L23/00 , H01L23/31 , H01L23/29 , H01L23/495
CPC分类号： H01L23/562 , H01L23/293 , H01L23/3114 , H01L23/3121 , H01L23/49513 , H01L23/4952 , H01L23/49524 , H01L23/49541 , H01L23/49582 , H01L23/49861 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/32227 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/12042 , H01L2924/15787 , H01L2924/181 , Y10T29/49155 , H01L2224/85 , H01L2224/81 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package includes a dielectric layer, a plurality of traces, a plurality of electrical pads, a plurality of studs and at least a semiconductor device. The dielectric layer has a first dielectric surface and a second dielectric surface opposite the first dielectric surface. The traces are disposed in the dielectric layer and are exposed on the second dielectric surface. The electrical pads are disposed on the first dielectric surface. The studs are disposed in the dielectric layer and are exposed on the first dielectric surface. The studs are electrically connected to the traces and the electrical pads. The semiconductor device is disposed on the second dielectric surface and electrically connected to the traces.
摘要翻译：半导体封装包括电介质层，多个迹线，多个电焊盘，多个螺柱和至少一个半导体器件。电介质层具有与第一电介质表面相对的第一电介质表面和第二电介质表面。迹线设置在电介质层中并暴露在第二电介质表面上。电焊盘设置在第一电介质表面上。螺柱设置在电介质层中并暴露在第一电介质表面上。螺柱电连接到迹线和电焊盘。半导体器件设置在第二电介质表面上并电连接到迹线。

4. 发明授权

US09305868B2 Manufacturing method of forming an etch-back type semiconductor package with locking anchorages 有权
标题翻译：形成具有锁定锚固件的回蚀式半导体封装的制造方法
公开(公告)号：US09305868B2
公开(公告)日：2016-04-05
申请号：US14579747
申请日：2014-12-22
申请人： ADVANPACK SOLUTIONS PTE LTD.
发明人： Hwee-Seng Jimmy Chew , Shoa-Siong Lim , Kian-Hock Lim
IPC分类号： H05K7/10 , H05K7/12 , H01L23/495 , H01L21/48 , H01L21/683 , H01L21/56 , H01L23/31 , H01L23/00
CPC分类号： H01L23/49503 , H01L21/4821 , H01L21/4832 , H01L21/56 , H01L21/561 , H01L21/6835 , H01L23/3107 , H01L23/49548 , H01L23/49582 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/83 , H01L24/85 , H01L24/97 , H01L2224/27013 , H01L2224/2919 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48253 , H01L2224/48611 , H01L2224/48639 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2224/48664 , H01L2224/73265 , H01L2224/83051 , H01L2224/83101 , H01L2224/83855 , H01L2224/85001 , H01L2224/85411 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/85464 , H01L2224/92 , H01L2224/92247 , H01L2224/97 , H01L2924/01006 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/10253 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package, a substrate and a manufacturing method thereof are provided. The substrate comprises a conductive carrier, a first metal layer and a second metal layer. The first metal layer is formed on the conductive carrier and comprises an lead pad having an upper surface. The second metal layer is formed on the first metal layer and comprises a bond pad. The bond pad overlaps and is in contact with the upper surface of the first metal layer. The upper surface of the lead pad is partially exposed. A part of the bond pad overhang outward from the edge of the lead pad.
摘要翻译：提供半导体封装，基板及其制造方法。衬底包括导电载体，第一金属层和第二金属层。第一金属层形成在导电载体上并且包括具有上表面的引线焊盘。第二金属层形成在第一金属层上并且包括接合焊盘。接合焊盘重叠并与第一金属层的上表面接触。引线板的上表面部分露出。接合焊盘的一部分从引线焊盘的边缘向外突出。

5. 发明授权

US08796844B2 Package structure 有权
标题翻译：包装结构
公开(公告)号：US08796844B2
公开(公告)日：2014-08-05
申请号：US13393746
申请日：2009-09-02
申请人： Hwee-Seng Jimmy Chew , Chee Kian Ong
发明人： Hwee-Seng Jimmy Chew , Chee Kian Ong
IPC分类号： H01L23/02 , H01L23/34 , H05K1/02 , H01L25/065 , H01L23/538
CPC分类号： H01L25/0655 , H01L23/5386 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2924/00014 , H01L2924/09701 , H01L2924/15311 , H05K1/0243 , H05K2201/10378 , H05K2201/10522 , H05K2201/10674 , H01L2224/0401
摘要： A package structure including a first semiconductor element, a second semiconductor element, a semiconductor interposer and a substrate is provided. The first semiconductor element includes multiple first conductive bumps. The second semiconductor element includes multiple second conductive bumps. The semiconductor interposer includes a connection motherboard, at least one signal wire and at least one signal conductive column. The signal wire is disposed on the connection motherboard. The two ends of the signal wire are electrically connected to one of the first conductive bumps and one of the second conductive bumps respectively. The signal conductive column is electrically connected to the signal wire. The substrate is electrically connected to the signal conductive column. The first and the second semiconductor elements have the same circuit structure. The substrate of the package structure can simultaneously form a signal communication path with the first and the second semiconductor element respectively.
摘要翻译：提供包括第一半导体元件，第二半导体元件，半导体插入器和基板的封装结构。第一半导体元件包括多个第一导电凸块。第二半导体元件包括多个第二导电凸块。半导体插入器包括连接母板，至少一个信号线和至少一个信号导电柱。信号线设置在连接母板上。信号线的两端分别电连接到第一导电凸块中的一个和第二导电凸块中的一个。信号导电柱与信号线电连接。衬底电连接到信号导电柱。第一和第二半导体元件具有相同的电路结构。封装结构的衬底可以分别同时形成与第一和第二半导体元件的信号通信路径。

6. 发明申请

US20110049708A1 Semiconductor Chip Interconnection Structure and Semiconductor Package Formed Using the Same 审中-公开
标题翻译：半导体芯片互连结构和使用其形成的半导体封装
公开(公告)号：US20110049708A1
公开(公告)日：2011-03-03
申请号：US12870216
申请日：2010-08-27
申请人： Lim Shoa Siong , Lim Kian Hock , Chew Hwee-Seng Jimmy
发明人： Lim Shoa Siong , Lim Kian Hock , Chew Hwee-Seng Jimmy
IPC分类号： H01L23/58
CPC分类号： H01L24/11 , H01L24/13 , H01L24/81 , H01L2224/1134 , H01L2224/13016 , H01L2224/13022 , H01L2224/1308 , H01L2224/13083 , H01L2224/13084 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/1357 , H01L2224/13644 , H01L2224/13655 , H01L2224/8121 , H01L2224/81815 , H01L2924/00013 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/3025 , H01L2924/00014 , H01L2224/13099
摘要： A semiconductor chip interconnection structure and a semiconductor package formed using the same are provided. The semiconductor chip interconnection structure comprises a chip, a bump assembly and an electrical element. The chip comprises a pad and has a pad aperture from which the pad is exposed. The bump assembly comprises a first bump and a second bump. The first bump is disposed on the pad. The second bump is disposed on the first bump. The outer diameter of the second bump is not less than the outer diameter of the first bump. The electrical element is connected to the bump assembly.
摘要翻译：提供半导体芯片互连结构和使用其形成的半导体封装。半导体芯片互连结构包括芯片，凸块组件和电气元件。芯片包括焊盘并具有焊盘孔，焊盘从该孔开始露出。凸块组件包括第一凸块和第二凸块。第一凸块设置在垫上。第二凸块设置在第一凸块上。第二凸块的外径不小于第一凸块的外径。电气元件连接到凸块组件。

7. 发明申请

US20060180888A1 Optical sensor package and method of manufacture 审中-公开
标题翻译：光传感器封装及其制造方法
公开(公告)号：US20060180888A1
公开(公告)日：2006-08-17
申请号：US11057646
申请日：2005-02-14
申请人： Teck Tan , Hwee Chew
发明人： Teck Tan , Hwee Chew
IPC分类号： H01L31/0203
CPC分类号： H01L27/14618 , H01L27/14625 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor package for optical sensing and method of manufacture thereof is disclosed. The semiconductor package comprises a substrate for transmitting radiation and an integrated circuit chip for sensing the radiation. A plurality of connectors for electrical transmission is disposed on the substrate and a plurality of pillars for facilitating electrical communication between the plurality of connectors and the integrated circuit chip is disposed between at least one of the plurality of connectors and the integrated circuit chip.
摘要翻译：公开了一种用于光学传感的半导体封装及其制造方法。半导体封装包括用于发射辐射的衬底和用于感测辐射的集成电路芯片。用于电传输的多个连接器设置在基板上，并且用于促进多个连接器和集成电路芯片之间的电连通的多个支柱设置在多个连接器和集成电路芯片中的至少一个之间。

8. 发明申请

US20050133933A1 Various structure/height bumps for wafer level-chip scale package 审中-公开
标题翻译：用于晶片级芯片级封装的各种结构/高度凸块
公开(公告)号：US20050133933A1
公开(公告)日：2005-06-23
申请号：US10742306
申请日：2003-12-19
申请人： Chng Shen , Matthew Han
发明人： Chng Shen , Matthew Han
IPC分类号： H01L21/56 , H01L23/29 , H01L23/31 , H01L23/48 , H01L23/485 , H01L23/488 , H01L23/60 , H01L25/065
CPC分类号： H01L24/10 , H01L23/3114 , H01L24/13 , H01L25/0657 , H01L2224/0401 , H01L2224/0603 , H01L2224/13 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2224/1403 , H01L2224/16145 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01057 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/30107 , H01L2924/3025 , H01L2224/29099 , H01L2924/00
摘要： A die comprising: a substrate; two or more various shaped bump structures having a solder line formed over the substrate; and an epoxy layer formed over the substrate. The epoxy layer having a top surface wherein: (a) the solder lines are below the top surface of the epoxy layer′; (b) the solder lines are above the top surface of the epoxy layer; or (c) some of the solder lines are below the top surface of the epoxy layer and some of the solder lines are above the top surface of the epoxy layer.
摘要翻译：一种模具，包括：基材; 两个或更多个具有在衬底上形成的焊料线的各种形状的凸起结构; 以及在基板上形成的环氧树脂层。环氧树脂层具有顶表面，其中：（a）焊接线在环氧树脂层的顶表面下方; （b）焊接线在环氧树脂层的顶表面之上; 或（c）一些焊接线在环氧树脂层的顶表面下方，并且一些焊接线在环氧树脂层的顶表面之上。

9. 发明申请

US20040053445A1 Method of assembling a package with an exposed die backside with and without a heatsink for flip-chip 有权
公开(公告)号：US20040053445A1
公开(公告)日：2004-03-18
申请号：US10243437
申请日：2002-09-13
申请人： Advanpack Solutions Pte. Ltd.
发明人： John Briar , Roman Perez , Tan Kim Hwee
IPC分类号： H01L021/44 , H01L021/48 , H01L021/50
CPC分类号： H01L23/36 , H01L23/3107 , H01L2224/05573 , H01L2224/16 , H01L2924/10253 , H01L2924/00 , H01L2224/05647 , H01L2924/00014
摘要： A method of assembling a package having an exposed die comprising the following steps. A die attached to a substrate by connectors is provided. The die having a backside. Encapsulate is formed around the die and over the backside of the die to form an encapsulated package. The encapsulate overlying the backside of the die and a portion of the backside of the die are removed using a backside exposure process to complete the assembled package having the die exposed.

10. 发明申请

US20040046238A1 Semiconductor chip grid array package design and method of manufacture 有权
标题翻译：半导体芯片阵列封装设计及制造方法
公开(公告)号：US20040046238A1
公开(公告)日：2004-03-11
申请号：US10236385
申请日：2002-09-06
申请人： Advanpack Solutions Pte Ltd.
发明人： Tan Kim Hwee , Roman Perez , Kee Kwang Lau , Alex Chew , Antonio Dimaano
IPC分类号： H01L021/44 , H01L023/02 , H01L029/40
CPC分类号： H01L21/6835 , H01L21/565 , H01L21/568 , H01L23/3114 , H01L24/11 , H01L24/12 , H01L2224/05573 , H01L2224/1147 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/13147 , H01L2924/00013 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01076 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/15747 , H01L2924/181 , H05K3/3436 , H05K3/3452 , H05K2201/09045 , Y02P70/613 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2224/05647
摘要： A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is.
摘要翻译：描述了利用CGA的芯片级封装。具有支柱的半导体芯片被模制在密封剂中。焊球被添加并连接到芯片支柱。最终包装不需要第一级基板或插入件，并且能够按原样组装到一个新的水平。

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