专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130036246A1 MICROCONTROLLER SYSTEM BUS SCHEDULING FOR MULTIPORT SLAVE MODULES 有权
标题翻译：微控制器系统总线调度用于多个从模块
公开(公告)号：US20130036246A1
公开(公告)日：2013-02-07
申请号：US13197547
申请日：2011-08-03
申请人： Franck Lunadier
发明人： Franck Lunadier
IPC分类号： G06F13/30 , G06F13/362 , G06F13/14
CPC分类号： G06F13/1605 , G06F13/36
摘要： A system includes master modules, at least one multiport slave module, and a scheduler connected by a system bus. The scheduler is configured to provide scheduling information to the multiport slave module. The scheduling information includes master categorization information and anticipated burst information. The anticipated burst information is based on a scheduler determination for an anticipated bus access by an anticipated master module. The master categorization information categorizes the anticipated master.
摘要翻译：系统包括主模块，至少一个多端口从站模块和通过系统总线连接的调度器。调度器被配置为向多端口从站模块提供调度信息。调度信息包括主分类信息和预期突发信息。预期突发信息基于预期主模块对于预期总线访问的调度器确定。主分类信息对预期的主人进行分类。

2. 发明申请

US20110138141A1 EXECUTE ONLY ACCESS RIGHTS ON A VON NEUMAN ARCHITECTURES 有权
标题翻译：执行唯一的访问权利在一个VON NEUMAN ARCHITECTURES
公开(公告)号：US20110138141A1
公开(公告)日：2011-06-09
申请号：US13028756
申请日：2011-02-16
申请人： Sandrine Batifoulier , Stephane Godzinski , Vincent Dupaquis
发明人： Sandrine Batifoulier , Stephane Godzinski , Vincent Dupaquis
IPC分类号： G06F12/14
CPC分类号： G06F12/1441
摘要： A microcontroller system, such as a system-on-a-chip integrated circuit, including a processor (e.g., a Von Neumann processor), memory, and a memory protection unit (MPU), where the MPU provides execute-only access rights for one or more protected areas of the memory. The MPU can allow instructions fetched from within a protected area to access data in the protected area while preventing instructions fetched from outside the protected area from accessing data in the protected area.
摘要翻译：诸如片上系统集成电路的微控制器系统，包括处理器（例如，冯诺依曼处理器），存储器和存储器保护单元（MPU），其中MPU提供仅执行访问权限存储器的一个或多个保护区域。 MPU可以允许从保护区域内取出的指令访问受保护区域中的数据，同时防止从保护区域外部取出的指令访问保护区域中的数据。

3. 发明授权

US07848515B2 Encryption protection method 有权
标题翻译：加密保护方法
公开(公告)号：US07848515B2
公开(公告)日：2010-12-07
申请号：US11358979
申请日：2006-02-22
申请人： Vincent Dupaquis , Michel Douguet
发明人： Vincent Dupaquis , Michel Douguet
IPC分类号： H04L9/28
CPC分类号： H04L9/0625 , H04L9/002 , H04L9/003 , H04L2209/043 , H04L2209/08 , H04L2209/24
摘要： A deterministic blinding method for cipher algorithms that employ key-mixing and substitution (S-box) operations uses a masking table constructed with a true mask and a plurality of dummy masks corresponding to every possible S-box input. Each mask is applied in the key-mixing operation (e.g., bitwise XOR) to the cipher key or to round subkeys to generate true and dummy keys or subkeys that are applied to the data blocks within the overall cipher algorithm or within individual cipher rounds. The mask values prevent side-channel statistical analyses from determining the true from the dummy keys or subkeys. The true mask is identifiable to the cipher but not by external observers.
摘要翻译：使用密钥混合和替代（S-box）操作的密码算法的确定性盲法使用由真实掩码和与每个可能的S盒输入相对应的多个伪掩码构成的掩蔽表。在密钥混合操作（例如，按位XOR）中对每个掩码应用于密码密钥或舍入子密钥以生成应用于整个加密算法内的数据块或单个密码轮内的真密钥或子密钥。掩码值可以防止侧信道统计分析从虚拟键或子键确定真。真正的掩码是可识别的，而不是外部观察者。

4. 发明授权

US07845568B2 Managing power and timing in a smart card device 有权
标题翻译：管理智能卡设备的电源和时序
公开(公告)号：US07845568B2
公开(公告)日：2010-12-07
申请号：US11746311
申请日：2007-05-09
申请人： Dominique Parlange , Jean Pierre Enguent , Romain Palmade
发明人： Dominique Parlange , Jean Pierre Enguent , Romain Palmade
IPC分类号： H04M11/00 , G06K19/07
CPC分类号： G06K19/0723 , G06K19/0701 , G06K19/0775
摘要： In some implementations, a mobile device includes a first interface configured to communicably couple to a removable integrated circuit card; a second interface configured to wirelessly communicate with a contactless reader that is external to the mobile device; a communication interface that couples the first interface and the second interface and that is configured to obtain information from an integrated circuit card that is coupled to the first interface in response to receipt by the second interface of an information request from the contactless reader; and a programmable timer that is configured to be started in response to the second interface receiving an information request from the contactless reader, and that is further configured to, upon reaching a programmed value, cause the second interface to transmit the obtained information to the contactless reader.
摘要翻译：在一些实施方案中，移动设备包括被配置为可通信地耦合到可移除集成电路卡的第一接口; 第二接口，被配置为与所述移动设备外部的非接触式读取器无线通信; 通信接口，其耦合所述第一接口和所述第二接口，并且被配置为响应于所述第二接口接收到来自所述非接触式读取器的信息请求而从耦合到所述第一接口的集成电路卡获取信息; 以及可编程定时器，被配置为响应于所述第二接口从所述非接触式读取器接收到信息请求而启动，并且还被配置为在达到编程值时使所述第二接口将所获得的信息发送到所述非接触式读者。

5. 发明授权

US08729629B2 Enhanced HVPMOS 有权
标题翻译：增强HVPMOS
公开(公告)号：US08729629B2
公开(公告)日：2014-05-20
申请号：US13539033
申请日：2012-06-29
申请人： Willem-Jan Toren , Bruno Villard , Elsa Hugonnard-Bruyere , Gaetan Toulon , Frederic Morancho , Ignasi Cortes Mayol , Thierry Pedron
发明人： Willem-Jan Toren , Bruno Villard , Elsa Hugonnard-Bruyere , Gaetan Toulon , Frederic Morancho , Ignasi Cortes Mayol , Thierry Pedron
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7824 , H01L29/063 , H01L29/0653 , H01L29/1083 , H01L29/1095 , H01L29/66681
摘要： A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-well diffusion, thus providing an evacuation path for electrons generated by impact ionization. High immunity to the Kirk effect is also achieved, resulting in a significantly improved safe-operating-area (SOA). The addition of the NBL deep inside the drift region supports a space-charge depletion region which increases the RESURF effectiveness, thus improving BV. An optimum NBL implanted dose can be set to ensure fully compensated charge balance among n and p doping in the drift region (charge balance conditions). The p-well implanted dose can be further increased to maintain a charge balance, which leads to an Rdson reduction.
摘要翻译：公开了具有受控n型掩埋层（NBL）的p沟道LDMOS器件。定义浅沟槽隔离（STI）氧化，部分或全部覆盖漂移区域长度。可以用p阱掩模定义的NBL层连接到n阱扩散，从而为通过冲击电离产生的电子提供排气路径。对Kirk效应的高度免疫力也得以实现，从而大大改善了安全操作区（SOA）。漂移区内部NBL的加入支持空间电荷耗尽区，增加了RESURF的有效性，从而改善了BV。可以设置最佳NBL植入剂量，以确保在漂移区域（电荷平衡条件）中n和p掺杂之间的完全补偿电荷平衡。可以进一步增加p阱注入剂量以维持电荷平衡，这导致Rdson降低。

6. 发明授权

US08601197B2 Microcontroller including flexible connections between modules 有权
标题翻译：微控制器包括模块之间的灵活连接
公开(公告)号：US08601197B2
公开(公告)日：2013-12-03
申请号：US12946699
申请日：2010-11-15
申请人： Alain Vergnes , Renaud Tiennot , Guillaume Pean
发明人： Alain Vergnes , Renaud Tiennot , Guillaume Pean
IPC分类号： G06F13/36
CPC分类号： G06F13/4022
摘要： A microcontroller includes a system bus matrix to connect various modules. The microcontroller also includes direct connections between modules. For example, the microcontroller may include a direct connection between a data processing module and a memory controller module to improve the transfer rate for data that is processed by the data processing module.
摘要翻译：微控制器包括用于连接各种模块的系统总线矩阵。微控制器还包括模块之间的直接连接。例如，微控制器可以包括数据处理模块和存储器控制器模块之间的直接连接，以提高由数据处理模块处理的数据的传输速率。

7. 发明授权

US08471636B2 Differential pair with constant offset 有权
标题翻译：具有恒定偏移的差分对
公开(公告)号：US08471636B2
公开(公告)日：2013-06-25
申请号：US13414145
申请日：2012-03-07
申请人： Jimmy Fort , Thierry Soude , Michel Cuenca , Florent Garcia , Franck Strazzieri
发明人： Jimmy Fort , Thierry Soude , Michel Cuenca , Florent Garcia , Franck Strazzieri
IPC分类号： H03F3/45
CPC分类号： H03F3/45179 , G05F3/245 , H03F3/45632 , H03F2200/447 , H03F2203/45101 , H03F2203/45482
摘要： A bias current is generated for an unbalanced differential pair that is proportional to the transconductance gain of the differential pair. When the transconductance gain varies (e.g., due to temperature variations), the bias current varies in proportion thereby maintaining a constant offset voltage. In some implementations, a voltage to current converter circuit generates the bias current from a constant reference voltage that is independent of temperature and voltage supply variations (e.g., a bandgap reference voltage).
摘要翻译：对于与差分对的跨导增益成比例的不平衡差分对产生偏置电流。当跨导增益变化（例如，由于温度变化）时，偏置电流按比例变化，从而保持恒定的偏移电压。在一些实施方式中，电压 - 电流转换器电路从与温度和电压供应变化（例如，带隙参考电压）无关的恒定参考电压产生偏置电流。

8. 发明授权

US08244959B2 Software adapted wear leveling 有权
标题翻译：软件适应磨损均匀
公开(公告)号：US08244959B2
公开(公告)日：2012-08-14
申请号：US12268383
申请日：2008-11-10
申请人： Yves Fusella , Stephane Godzinski , Laurent Paris , Jean-Pascal Maraninchi , Samuel Charbouillot
发明人： Yves Fusella , Stephane Godzinski , Laurent Paris , Jean-Pascal Maraninchi , Samuel Charbouillot
IPC分类号： G11C11/34 , G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7211
摘要： A subset of software objects stored in a first segment of non-volatile memory are identified as requiring frequent write operations or otherwise associated with a high endurance requirement. The subset of software objects are move to a second segment of non-volatile memory with a high endurance capacity, due to the application of wear leveling techniques to the second segment of non-volatile memory. The first and second segments of memory can be located in the same memory device or different memory devices.
摘要翻译：存储在非易失性存储器的第一段中的软件对象的子集被标识为需要频繁写入操作或以其他方式与高耐久性要求相关联。由于在非易失性存储器的第二段应用了磨损均衡技术，软件对象的子集移动到具有高耐久容量的非易失性存储器的第二段。存储器的第一和第二段可以位于相同的存储器件或不同的存储器件中。

9. 发明授权

US08217452B2 Enhanced HVPMOS 有权
标题翻译：增强HVPMOS
公开(公告)号：US08217452B2
公开(公告)日：2012-07-10
申请号：US12851256
申请日：2010-08-05
申请人： Willem-Jan Toren , Bruno Villard , Elsa Hugonnard-Bruyere , Gaetan Toulon , Frederic Morancho , Ignasi Cortes Mayol , Thierry Pedron
发明人： Willem-Jan Toren , Bruno Villard , Elsa Hugonnard-Bruyere , Gaetan Toulon , Frederic Morancho , Ignasi Cortes Mayol , Thierry Pedron
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7824 , H01L29/063 , H01L29/0653 , H01L29/1083 , H01L29/1095 , H01L29/66681
摘要： A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-well diffusion, thus providing an evacuation path for electrons generated by impact ionization. High immunity to the Kirk effect is also achieved, resulting in a significantly improved safe-operating-area (SOA). The addition of the NBL deep inside the drift region supports a space-charge depletion region which increases the RESURF effectiveness, thus improving BV. An optimum NBL implanted dose can be set to ensure fully compensated charge balance among n and p doping in the drift region (charge balance conditions). The p-well implanted dose can be further increased to maintain a charge balance, which leads to an Rdson reduction.
摘要翻译：公开了具有受控n型掩埋层（NBL）的p沟道LDMOS器件。定义浅沟槽隔离（STI）氧化，部分或全部覆盖漂移区域长度。可以用p阱掩模定义的NBL层连接到n阱扩散，从而为通过冲击电离产生的电子提供排气路径。对Kirk效应的高度免疫力也得以实现，从而大大改善了安全操作区（SOA）。漂移区内部NBL的加入支持空间电荷耗尽区，增加了RESURF的有效性，从而改善了BV。可以设置最佳NBL植入剂量，以确保在漂移区域（电荷平衡条件）中n和p掺杂之间的完全补偿电荷平衡。可以进一步增加p阱注入剂量以维持电荷平衡，这导致Rdson降低。

10. 发明授权

US08214729B2 Error detecting/correcting scheme for memories 有权
公开(公告)号：US08214729B2
公开(公告)日：2012-07-03
申请号：US13335725
申请日：2011-12-22
申请人： Godard Benoit , Jean Michel Daga
发明人： Godard Benoit , Jean Michel Daga
IPC分类号： G06F11/00 , H03M13/00 , G11C29/00
CPC分类号： G06F11/1068 , G11C2029/0411
摘要： A method for detecting and correcting errors in a memory having a read/write paradigm is presented. In these implementations, various approaches to detect errors on a per word or per group of words basis and correct errors on a per group of words or per page basis, respectively, in relation to a memory and its associated differing read/write operations, are provided. For instance, in one implementation, errors are detected on a per word basis and corrected on a per page basis for a NOR Flash Memory having differing read/write operations of reading on a per word basis and writing on a per page basis. Advantageously, benefits of the various implementations include reduced encoder/decoder complexities, reduced parity overhead requirements, and reduced performance degradation.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式