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1. 发明申请

US20150228710A1 Methods to Improve Electrical Performance of ZrO2 Based High-K Dielectric Materials for DRAM Applications 有权
标题翻译：改善用于DRAM应用的ZrO2基高K介电材料的电性能的方法
公开(公告)号：US20150228710A1
公开(公告)日：2015-08-13
申请号：US14177118
申请日：2014-02-10
申请人： Elpida Memory, Inc , Intermolecular, Inc.
发明人： Xiangxin Rui , Hanhong Chen , Naonori Fujiwara , Imran Hashim , Kenichi Koyanagi
IPC分类号： H01L49/02 , H01L27/108
CPC分类号： H01L28/40 , H01G4/10 , H01G4/1236 , H01G4/33 , H01L27/10805 , H01L27/1085 , H01L28/56 , H01L28/75
摘要： A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly-doped or non-doped material. The highly doped material will remain amorphous (
摘要翻译：用于减少DRAM MIM电容器中的漏电流的方法包括从非晶高掺杂材料，非晶高带隙材料和轻掺杂或非掺杂材料形成多层电介质叠层。退火步骤后，高掺杂材料将保持无定形（<30％结晶）。在退火步骤之后，高带隙材料将保持无定形（<30％结晶）。在退火步骤之后，轻掺杂或非掺杂材料将变成晶体（≥30％结晶）。高带隙材料形成在无定形高掺杂材料和轻掺杂材料和非掺杂材料之间，并提供通过多层电介质叠层的导电的中间屏障。

2. 发明申请

US20150149717A1 PARTIAL ACCESS MODE FOR DYNAMIC RANDOM ACCESS MEMORY 有权
标题翻译：动态随机访问存储器的部分访问模式
公开(公告)号：US20150149717A1
公开(公告)日：2015-05-28
申请号：US14168899
申请日：2014-01-30
申请人： Micron Technology, Inc.
发明人： Yoshiro RIHO
IPC分类号： G11C11/406
CPC分类号： G11C11/40615 , G11C11/40622
摘要： Some embodiments provide a method to reduce the refresh power consumption by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2N cells/bit reduces the variation in the retention time among memory cells. Although active power increases by a factor of 2N, the refresh time increases by more than 2N as a consequence of the fact that the majority decision does better than averaging for the tail distribution of retention time. The conversion can be realized very simply from the structure of the DRAM array circuit, and it reduces the frequency of disturbance and power consumption by two orders of magnitude. On the basis of this conversion method, some embodiments provide a partial access mode to reduce power consumption dynamically when the full memory capacity is not required.
摘要翻译：一些实施例提供了通过有效地延长存储器单元保留时间来减少刷新功率消耗的方法。从1个单元/位转换为2N个单元/位减少了存储单元之间的保留时间的变化。虽然有功功率增加了2N倍，但是由于多数决定比保留时间的尾部分布的平均值更好，所以刷新时间增加了2N以上。可以从DRAM阵列电路的结构非常简单地实现转换，并且将干扰和功耗的频率降低两个数量级。基于该转换方法，一些实施例提供了部分访问模式，以便在不需要全存储器容量时动态地降低功耗。

3. 发明授权

US08980744B2 Inexpensive electrode materials to facilitate rutile phase titanium oxide 有权
标题翻译：廉价的电极材料，以促进金红石相氧化钛
公开(公告)号：US08980744B2
公开(公告)日：2015-03-17
申请号：US13675852
申请日：2012-11-13
申请人： Intermolecular, Inc.
发明人： Hanhong Chen , Toshiyuki Hirota , Pragati Kumar , Xiangxin Rui , Sunil Shanker
IPC分类号： H01L27/108 , H01L49/02 , C23C16/40
CPC分类号： H01L28/60 , C23C16/405 , H01L27/10852 , H01L28/40
摘要： This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.
摘要翻译：本公开提供了制造半导体堆叠和相关设备（诸如电容器和DRAM单元）的方法。特别地，底部电极具有选择用于晶格匹配特性的材料。该材料可以由相对廉价的金属氧化物制成，其被处理成具有特定结晶形式的导电但难以产生的氧化物状态; 为了提供一个实例，公开了与用作电介质的金红石相二氧化钛（TiO 2）的生长相容的具体材料，从而导致可预测和可再现的较高介电常数和较低的有效氧化物厚度，因此更大的部分密度以较低的成本。

4. 发明授权

US08900422B2 Yttrium and titanium high-K dielectric film 有权
标题翻译：钇和钛高K电介质膜
公开(公告)号：US08900422B2
公开(公告)日：2014-12-02
申请号：US12921776
申请日：2009-04-17
申请人： Imran Hashim , Indranil De , Tony Chiang , Edward Haywood , Hanhong Chen , Nobi Fuchigami , Pragati Kumar , Sandra Malhotra , Sunil Shanker
发明人： Imran Hashim , Indranil De , Tony Chiang , Edward Haywood , Hanhong Chen , Nobi Fuchigami , Pragati Kumar , Sandra Malhotra , Sunil Shanker
IPC分类号： B05D5/12 , C23C14/34 , H01L49/02 , C23C16/40 , C23C16/455 , H01L21/314 , H01L21/316 , H01L27/108 , H01L21/02
CPC分类号： H01L28/65 , C23C16/405 , C23C16/45529 , C23C16/45531 , H01L21/02697 , H01L21/3141 , H01L21/31604 , H01L27/10852 , H01L28/40
摘要： This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.
摘要翻译：本公开内容提供（a）制造基于钇和钛的氧化物层（例如，电介质层）的方法，以具有高介电常数和低泄漏特性，以及（b）相关的器件和结构。具有钇和钛的氧化物层可以制成无定形氧化物或交替的单层系列。在几个实施方案中，氧化物的特征在于对特定控制的总金属的钇贡献。如果需要，可以通过PVD工艺或者通过使用特定的前体材料以允许钛和钇的共同工艺温度窗口的原子层沉积工艺，作为反应过程的结果来生产氧化物层反应。

5. 发明申请

US20140241059A1 METHOD AND DEVICE FOR STORING AND READING RELIABLE INFORMATION IN A NAND ARRAY 有权
标题翻译：用于在NAND阵列中存储和读取可靠信息的方法和设备
公开(公告)号：US20140241059A1
公开(公告)日：2014-08-28
申请号：US13774756
申请日：2013-02-22
申请人： ELPIDA MEMORY, INC.
发明人： Giulio Martinozzi , Stefano Sivero
IPC分类号： G11C29/04 , G11C16/04
CPC分类号： G11C29/04 , G11C16/0408 , G11C16/20 , G11C16/349 , G11C29/76 , G11C2211/5642 , G11C2229/723
摘要： A method (and device) includes producing first data in a page region of a memory, the first data including a first number of memory sets, each of the memory sets having a second number of bits, where the first number is a positive number more than one and the second number is a positive number more than three. After the producing the first data in the page region of the memory, second data is produced in response to the produced first data, the second data having the first number of bits, each of the bits of the second data having a logic value that is determined by a majority of the bits included in a corresponding one of the memory sets.
摘要翻译：方法（和装置）包括在存储器的页面区域中产生第一数据，第一数据包括第一数量的存储器组，每个存储器组具有第二数量的位，其中第一个数是更多的正数超过一个，第二个数字是三个以上的正数。在产生存储器的页面区域中的第一数据之后，响应于所产生的第一数据产生第二数据，第二数据具有第一位数，第二数据的每个位具有逻辑值即由包括在相应的一个存储器组中的大部分位确定。

6. 发明申请

US20140233334A1 SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME 审中-公开
标题翻译：半导体器件及其控制方法
公开(公告)号：US20140233334A1
公开(公告)日：2014-08-21
申请号：US14263262
申请日：2014-04-28
申请人： Elpida Memory, Inc.
发明人： Kinu MATSUNAGA , Hiroshi AKAMATSU
IPC分类号： G11C7/12 , G11C7/22
CPC分类号： G11C7/12 , G11C7/222 , G11C11/401 , G11C11/4094 , G11C29/16
摘要： A device includes a command decoder that is configured to output, in a normal operation mode, a precharge signal in response to a first type transition edge of a synchronous signal, and an active signal in response to a next first type transition edge that is next to the first type transition edge. The command decoder is configured to output, in a test mode, the precharge signal in response to a second type transition edge of the synchronous signal, and the active signal in response to a next first type transition edge that is next to the second type transition edge.
摘要翻译：一种设备包括命令解码器，其被配置为在正常操作模式下响应于同步信号的第一类型转换边缘输出预充电信号，并响应于下一个第一类型转换边缘而输出下一个到第一类型的过渡边缘。命令解码器被配置为在测试模式下响应于同步信号的第二类型转换边沿而输出预充电信号，并且响应于接下来的第二类型转换的下一个第一类型转换边缘来输出有效信号边缘。

7. 发明授权

US08809160B2 Methods for forming high-K crystalline films and related devices 有权
标题翻译：用于形成高K晶体膜和相关器件的方法
公开(公告)号：US08809160B2
公开(公告)日：2014-08-19
申请号：US13334618
申请日：2011-12-22
申请人： Hanhong Chen , Edward Haywood , Pragati Kumar , Sandra G Malhotra , Xiangxin Rui
发明人： Hanhong Chen , Edward Haywood , Pragati Kumar , Sandra G Malhotra , Xiangxin Rui
IPC分类号： H01L21/20 , H01L21/31 , H01L21/02 , H01L49/02
CPC分类号： H01L28/40 , H01L21/02186 , H01L21/02189 , H01L21/0228 , H01L28/56 , H01L28/60
摘要： This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor or DRAM cell. In such a device, a high-K zirconia-based layer may be used as the primary dielectric together with a relatively inexpensive metal electrode based on titanium nitride. To prevent corruption of the electrode during device formation, a thin barrier layer can be used seal the electrode prior to the use of a high temperature process and a (high-concentration or dosage) ozone reagent (i.e., to create a high-K zirconia-based layer). In some embodiments, the barrier layer can also be zirconia-based, for example, a thin layer of doped or un-doped amorphous zirconia. Fabrication of a device in this manner facilitates formation of a device with dielectric constant of greater than 40 based on zirconia and titanium nitride, and generally helps produce less costly, increasingly dense DRAM cells and other semiconductor structures.
摘要翻译：本公开提供了制造半导体堆叠和相关联的器件（诸如电容器或DRAM单元）的方法。在这种器件中，高K氧化锆基层可以与基于氮化钛的相对廉价的金属电极一起用作主要电介质。为了防止在器件形成期间电极的损坏，可以使用薄的阻挡层，在使用高温工艺和（高浓度或剂量）的臭氧试剂之前密封电极（即，产生高K氧化锆基层）。在一些实施例中，阻挡层也可以是基于氧化锆的，例如掺杂或未掺杂的无定形氧化锆的薄层。以这种方式制造器件有助于基于氧化锆和氮化钛形成具有大于40的介电常数的器件，并且通常有助于产生更便宜的，越来越致密的DRAM电池和其它半导体结构。

8. 发明申请

US20140227855A1 SEMICONDUCTOR DEVICE HAVING GATE TRENCH AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：具有闸门开关的半导体器件及其制造方法
公开(公告)号：US20140227855A1
公开(公告)日：2014-08-14
申请号：US14258521
申请日：2014-04-22
申请人： Elpida Memory, Inc.
发明人： Wu NAN
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/823431 , H01L27/10876 , H01L27/10894
摘要： Disclosed herein is a semiconductor device that includes a trench formed across active regions and the element isolation regions. A conductive film is formed at a lower portion of the trench, and a cap insulating film is formed at an upper portion of the trench. The cap insulating film has substantially the same planer shape as that of the conductive film.
摘要翻译：本文公开了一种半导体器件，其包括横跨有源区域和元件隔离区域形成的沟槽。导电膜形成在沟槽的下部，并且在沟槽的上部形成帽绝缘膜。盖绝缘膜具有与导电膜基本相同的平面形状。

9. 发明申请

US20140226423A1 DEVICE 审中-公开
标题翻译：设备
公开(公告)号：US20140226423A1
公开(公告)日：2014-08-14
申请号：US14256051
申请日：2014-04-18
申请人： Elpida Memory, Inc.
发明人： Hiroshi AKAMATSU , Shoji Kaneko
IPC分类号： G11C29/00
CPC分类号： G11C29/00 , G11C5/147 , G11C7/10 , G11C7/109 , G11C7/12 , G11C7/22 , G11C7/222 , G11C8/08 , G11C8/18 , G11C11/4076 , G11C11/4085 , G11C29/023 , G11C29/12015 , G11C2029/1202
摘要： Provided is a device, including: a first terminal which receives an external clock signal; a clock generation circuit connected to the first terminal to generate an internal clock signal based on the external clock signal; word lines and bit lines; amplifier circuits connected to the bit lines, respectively; and a control unit. The control unit controls, in a test operation, at least one of the word lines to repeat a selected state and an unselected state in accordance with the internal clock signal during a first period, and maintains the amplifier circuits in an active state during the first period. The control unit further controls, in a normal operation, the amplifier circuits to switch between the active state and an inactive state depending on switching between the selected state and the unselected state of the at least one of the word lines.
摘要翻译：提供一种装置，包括：接收外部时钟信号的第一终端; 连接到第一终端的时钟发生电路，以基于外部时钟信号产生内部时钟信号; 字线和位线; 分别连接到位线的放大器电路; 和控制单元。控制单元在测试操作中控制至少一个字线，以在第一周期期间根据内部时钟信号重复所选择的状态和未选择状态，并且在第一时间段期间将放大器电路维持在活动状态期。控制单元在正常操作中进一步控制放大器电路根据所选择的状态和至少一个字线的未选择状态之间的切换而在有效状态和非活动状态之间切换。

10. 发明申请

US20140217560A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20140217560A1
公开(公告)日：2014-08-07
申请号：US14161248
申请日：2014-01-22
申请人： Elpida Memory, Inc.
发明人： Osamu FUJITA
IPC分类号： H01L23/48 , H01L23/538
CPC分类号： H01L23/481 , H01L21/30655 , H01L21/76898 , H01L21/823481 , H01L23/5384 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L27/0617 , H01L2224/0401 , H01L2224/05166 , H01L2224/05572 , H01L2224/05647 , H01L2224/11462 , H01L2224/13009 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2224/14181 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/81095 , H01L2224/81193 , H01L2224/81203 , H01L2224/81907 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/14335 , H01L2924/1436 , H01L2924/1437 , H01L2924/1438 , H01L2924/1461 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor device includes a semiconductor substrate having a first surface, a through silicon via (TSV) that is formed so that at least a part thereof penetrates through the semiconductor substrate, and an insulation ring. The insulation ring is formed so as to penetrate through the semiconductor substrate and so as to surround the TSV. The insulation ring includes a tapered portion and a vertical portion. The tapered portion has a sectional area which is gradually decreased from the first surface toward a thickness direction of the semiconductor substrate. The vertical portion has a constant sectional area smaller than the tapered portion.
摘要翻译：半导体器件包括具有第一表面的半导体衬底和形成为使得其至少一部分穿透半导体衬底的绝缘环的贯通硅通孔（TSV）。绝缘环形成为穿过半导体衬底并围绕TSV。绝缘环包括锥形部分和垂直部分。锥形部分具有从半导体衬底的第一表面朝向厚度方向逐渐减小的截面积。垂直部分具有比锥形部分小的恒定截面积。

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