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1. 发明授权

US09018750B2 Thin film structure for high density inductors and redistribution in wafer level packaging 有权
标题翻译：用于高密度电感器的薄膜结构和晶片级封装中的再分配
公开(公告)号：US09018750B2
公开(公告)日：2015-04-28
申请号：US13572376
申请日：2012-08-10
申请人： Robert Forcier , Douglas Scott
发明人： Robert Forcier , Douglas Scott
IPC分类号： H01L27/00 , H01L23/538 , H01L23/522 , H01L23/532 , H01L23/00 , H01L23/525
CPC分类号： H01L23/5389 , H01L23/5227 , H01L23/525 , H01L23/53223 , H01L24/19 , H01L2223/6677 , H01L2224/12105 , H01L2924/1461 , H01L2924/00
摘要： Disclosed is a package that includes a wafer substrate and a metal stack seed layer. The metal stack seed layer includes a titanium thin film outer layer. A resist layer is provided in contact with the titanium thin film outer layer of the metal stack seed layer, the resist layer forming circuitry. A method for manufacturing a package is further disclosed. A metal stack seed layer having a titanium thin film outer layer is formed. A resist layer is formed so as to be in contact with the titanium thin film outer layer of the metal stack seed layer, and circuitry is formed from the resist layer.
摘要翻译：公开了一种包括晶片衬底和金属堆叠种子层的封装。金属堆叠种子层包括钛薄膜外层。提供与金属堆叠种子层的钛薄膜外层，抗蚀剂层形成电路接触的抗蚀剂层。进一步公开了一种制造封装的方法。形成具有钛薄膜外层的金属堆叠种子层。形成抗蚀剂层以与金属堆叠种子层的钛薄膜外层接触，并且由抗蚀剂层形成电路。

2. 发明申请

US20110003470A1 METHODS AND STRUCTURES FOR A VERTICAL PILLAR INTERCONNECT 审中-公开
标题翻译：垂直柱连接的方法和结构
公开(公告)号：US20110003470A1
公开(公告)日：2011-01-06
申请号：US12828003
申请日：2010-06-30
申请人： Guy F. Burgess , Anthony Curtis , Michael E. Johnson , Gene Stout , Theodore G. Tessier
发明人： Guy F. Burgess , Anthony Curtis , Michael E. Johnson , Gene Stout , Theodore G. Tessier
IPC分类号： H01L21/768
CPC分类号： H01L24/11 , H01L21/563 , H01L24/03 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L2224/0345 , H01L2224/03464 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/1132 , H01L2224/11462 , H01L2224/1147 , H01L2224/11472 , H01L2224/11474 , H01L2224/11505 , H01L2224/1184 , H01L2224/11849 , H01L2224/119 , H01L2224/11901 , H01L2224/11903 , H01L2224/13012 , H01L2224/13013 , H01L2224/13014 , H01L2224/13024 , H01L2224/13082 , H01L2224/13083 , H01L2224/13101 , H01L2224/13111 , H01L2224/13116 , H01L2224/13117 , H01L2224/13118 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13294 , H01L2224/133 , H01L2224/13339 , H01L2224/1403 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/81191 , H01L2224/81815 , H01L2224/8184 , H01L2224/831 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01051 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/381 , H01L2924/01028 , H01L2924/0105 , H01L2924/01048 , H01L2924/01032 , H01L2924/00014 , H01L2924/00012
摘要： In wafer-level chip-scale packaging and flip-chip packaging and assemblies, a solder cap is formed on a vertical pillar. In one embodiment, the vertical pillar overlies a semiconductor substrate. A solder paste, which may be doped with at least one trace element, is applied on a top surface of the pillar structure. A reflow process is performed after applying the solder paste to provide the solder cap.
摘要翻译：在晶圆级芯片级封装和倒装芯片封装和组装中，在垂直支柱上形成焊锡帽。在一个实施例中，垂直柱覆盖半导体衬底。可以在柱结构的顶表面上施加可以掺杂有至少一个微量元素的焊膏。在施加焊膏以提供焊料盖之后进行回流工艺。

3. 发明申请

US20090057909A1 UNDER BUMP METALLIZATION STRUCTURE HAVING A SEED LAYER FOR ELECTROLESS NICKEL DEPOSITION 审中-公开
标题翻译：具有电解镍沉积物的种子层的下层金属结构
公开(公告)号：US20090057909A1
公开(公告)日：2009-03-05
申请号：US12142415
申请日：2008-06-19
申请人： Thomas Strothmann
发明人： Thomas Strothmann
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L23/3114 , H01L24/03 , H01L24/12 , H01L2224/03 , H01L2224/03914 , H01L2224/0401 , H01L2224/05552 , H01L2224/05554 , H01L2224/05555 , H01L2224/05568 , H01L2224/05572 , H01L2224/1147 , H01L2224/131 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2224/13099
摘要： Structures and methods for fabrication of an under bump metallization (UBM) structure having a metal seed layer and electroless nickel deposition layer are disclosed involving a UBM structure comprising a semiconductor substrate, at least one final metal layer, a passivation layer, a metal seed layer, and a metallization layer. The at least one final metal layer is formed over at least a portion of the semiconductor substrate. Also, the passivation layer is formed over at least a portion of the semiconductor substrate. In addition, the passivation layer includes a plurality of openings. Additionally, the passivation layer is formed of a non-conductive material. The at least one final metal layer is exposed through the plurality of openings. The metal seed layer is formed over the passivation layer and covers the plurality of openings. The metallization layer is formed over the metal seed layer. The metallization layer is formed from electroless deposition.
摘要翻译：公开了一种用于制造具有金属种子层和无电镀镍沉积层的凸块下金属化（UBM）结构的结构和方法，涉及包含半导体衬底，至少一个最终金属层，钝化层，金属种子层的UBM结构，以及金属化层。在半导体衬底的至少一部分上形成至少一个最终金属层。此外，钝化层形成在半导体衬底的至少一部分上。此外，钝化层包括多个开口。另外，钝化层由非导电材料形成。至少一个最终的金属层通过多个开口露出。金属种子层形成在钝化层上并覆盖多个开口。金属化层形成在金属种子层上。金属化层由无电沉积形成。

4. 发明授权

US07118833B2 Forming partial-depth features in polymer film 有权
标题翻译：在聚合物膜中形成部分深度特征
公开(公告)号：US07118833B2
公开(公告)日：2006-10-10
申请号：US10672201
申请日：2003-09-26
申请人： Peter Elenius , Michael E. Johnson
发明人： Peter Elenius , Michael E. Johnson
IPC分类号： G03F9/00 , G03C5/00
CPC分类号： G03F1/50
摘要： A photomask (1900) for producing partial-depth features (712 and 912) in a photo-imageable polymer layer (412) on a wafer of a chip scale package (200) using exposure tools capable of resolving sizes of a critical dimension or larger, has a plurality of chrome lines (2101–2103). Each chrome line has a width (2105) that is less than the critical dimension, and each chrome line of the plurality of chrome lines is spaced apart less than the critical dimension. The plurality of chrome lines produces a single partial-depth feature, such as a via, through part of a thickness of the polymer layer. Alternatively, the photomask has a plurality of chrome circles (2206), each chrome circle having a diameter less than the critical dimension and being spaced apart less than the critical dimension, which produces the partial-depth feature. The photomask may also have chrome of width greater than the critical dimension and spaced from other chrome by a distance greater than the critical dimension, which produces a full-depth feature through the entire thickness of the polymer film. The partial-depth feature and the full-depth feature are produced substantially simultaneously during a single series of photo-imaging steps. By preselecting a size, shape and distance between the chrome, the photomask is capable of inscribing discernable markings on the polymer layer, of changing the thickness of the polymer layer, and of changing an optical property of the surface of the polymer layer.
摘要翻译：一种光掩模（1900），用于使用能够分辨关键尺寸或更大尺寸的曝光工具在芯片级封装（200）的晶片上的可光成像聚合物层（412）中产生部分深度特征（712和912）具有多条铬线（2101-2103）。每个铬线具有小于临界尺寸的宽度（2105），并且多个铬线的每个铬线间隔开小于临界尺寸。多条铬线通过聚合物层的厚度的一部分产生单一部分深度特征，例如通孔。或者，光掩模具有多个铬圆（2206），每个铬圆的直径小于临界尺寸，并且间隔开小于临界尺寸，产生部分深度特征。光掩模还可以具有大于临界尺寸的宽度的铬，并且与其它铬隔开大于临界尺寸的距离，其通过聚合物膜的整个厚度产生全深度特征。部分深度特征和全深度特征在单个系列的光成像步骤期间基本上同时产生。通过预先选择铬之间的尺寸，形状和距离，光掩模能够在聚合物层上刻划可辨别的标记，改变聚合物层的厚度和改变聚合物层的表面的光学性质。

5. 发明申请

US20130244382A1 HIGH PRECISION SELF ALIGNING DIE FOR EMBEDDED DIE PACKAGING 审中-公开
标题翻译：高精度自动对准嵌入式包装
公开(公告)号：US20130244382A1
公开(公告)日：2013-09-19
申请号：US13618363
申请日：2012-09-14
申请人： David Clark
发明人： David Clark
IPC分类号： H01L21/56
CPC分类号： H01L21/56 , H01L23/49816 , H01L23/5389 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/81 , H01L2224/02379 , H01L2224/0401 , H01L2224/04105 , H01L2224/05024 , H01L2224/12105 , H01L2224/131 , H01L2224/16227 , H01L2224/73209 , H01L2224/81815 , H01L2924/12042 , H01L2924/18162 , H01L2924/00014 , H01L2924/014 , H01L2924/00
摘要： An apparatus and process for self-aligning components for forming an embedded die package is disclosed. The process includes providing a planar printed wire board (PWB) substrate having registration pads and a component having contact pads and spaced alignment pads, wherein the alignment pads each have a solder cap, placing the component on the substrate such that the alignment pads are in coarse alignment with the registration pads, applying heat to the alignment and registration pads to reflow the solder caps to precisely align the pads; and reducing the temperature below the reflow temperature. The process further includes applying a backside outer layer lamination, forming first vias, forming redistribution conductors on an opposite surface of the substrate connecting to the vias, and applying a front side outer layer lamination over the opposite surface of the substrate, all at temperatures below the reflow temperature.
摘要翻译：公开了一种用于形成嵌入式封装的自对准元件的装置和工艺。该方法包括提供具有配准焊盘和具有接触焊盘和间隔对准焊盘的部件的平面印刷线路板（PWB）基板，其中对准焊盘各自具有焊接帽，将部件放置在基板上，使得对准焊盘处于与对准焊盘粗略对准，向对准和对准焊盘施加热量以回流焊帽以精确对准焊盘; 并将温度降低到回流温度以下。该方法还包括施加背面外层层压，形成第一通孔，在连接到通孔的衬底的相对表面上形成再分布导体，以及在衬底的相对表面上施加前侧外层层压，全部在低于回流温度。

6. 发明授权

US08446019B2 Solder bump interconnect 有权
标题翻译：焊点互连
公开(公告)号：US08446019B2
公开(公告)日：2013-05-21
申请号：US13457311
申请日：2012-04-26
申请人： Reynante Alvarado , Yuan Lu , Richard Redburn
发明人： Reynante Alvarado , Yuan Lu , Richard Redburn
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L23/3171 , H01L23/3192 , H01L24/02 , H01L24/03 , H01L24/13 , H01L2224/0235 , H01L2224/0239 , H01L2224/0345 , H01L2224/0346 , H01L2224/0401 , H01L2224/04042 , H01L2224/05022 , H01L2224/05073 , H01L2224/05124 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05541 , H01L2224/05548 , H01L2224/05554 , H01L2224/05555 , H01L2224/05567 , H01L2224/05572 , H01L2224/0558 , H01L2224/05644 , H01L2224/05647 , H01L2224/05666 , H01L2224/1148 , H01L2224/13006 , H01L2224/13007 , H01L2224/13021 , H01L2224/13022 , H01L2224/131 , H01L2224/45144 , H01L2224/45147 , H01L2224/48644 , H01L2224/48647 , H01L2224/48666 , H01L2224/48844 , H01L2224/48847 , H01L2224/48866 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/351 , H01L2924/00014 , H01L2924/00015 , H01L2224/13099 , H01L2924/00
摘要： A semiconductor package includes a device pad on a substrate. A first polymer layer overlies the substrate, and the first polymer layer has an opening to expose the device pad. In one embodiment, a redistribution layer (RDL) comprises a landing pad, and the RDL is positioned on the first polymer layer and conductively coupled to the device pad. A second polymer layer is on the RDL, and an under bump metal pad (UBM) is on the landing pad and extends onto a top surface of the second polymer layer. In one embodiment, a shortest distance from a center of the landing pad to an outer edge of the landing pad, and a shortest distance from a center of the UBM to an outer edge of the UBM are in a ratio that ranges from 0.5:1 up to 0.95:1.
摘要翻译：半导体封装包括在衬底上的器件焊盘。第一聚合物层覆盖在基底上，第一聚合物层具有露出装置垫的开口。在一个实施例中，再分配层（RDL）包括着陆焊盘，并且RDL定位在第一聚合物层上并且导电地耦合到器件焊盘。第二聚合物层位于RDL上，下凸块金属垫（UBM）在着陆垫上并延伸到第二聚合物层的顶表面上。在一个实施例中，从着陆焊盘的中心到着陆焊盘的外边缘的最短距离以及从UBM的中心到UBM的外边缘的最短距离的范围为0.5:1 高达0.95：1。

7. 发明申请

US20120228765A1 SOLDER BUMP INTERCONNECT 有权
标题翻译：焊接块互连
公开(公告)号：US20120228765A1
公开(公告)日：2012-09-13
申请号：US13457311
申请日：2012-04-26
申请人： Reynante Alvarado , Yuan Lu , Richard Redburn
发明人： Reynante Alvarado , Yuan Lu , Richard Redburn
IPC分类号： H01L23/485
CPC分类号： H01L24/05 , H01L23/3171 , H01L23/3192 , H01L24/02 , H01L24/03 , H01L24/13 , H01L2224/0235 , H01L2224/0239 , H01L2224/0345 , H01L2224/0346 , H01L2224/0401 , H01L2224/04042 , H01L2224/05022 , H01L2224/05073 , H01L2224/05124 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05541 , H01L2224/05548 , H01L2224/05554 , H01L2224/05555 , H01L2224/05567 , H01L2224/05572 , H01L2224/0558 , H01L2224/05644 , H01L2224/05647 , H01L2224/05666 , H01L2224/1148 , H01L2224/13006 , H01L2224/13007 , H01L2224/13021 , H01L2224/13022 , H01L2224/131 , H01L2224/45144 , H01L2224/45147 , H01L2224/48644 , H01L2224/48647 , H01L2224/48666 , H01L2224/48844 , H01L2224/48847 , H01L2224/48866 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/351 , H01L2924/00014 , H01L2924/00015 , H01L2224/13099 , H01L2924/00
摘要： A semiconductor package includes a device pad on a substrate. A first polymer layer overlies the substrate, and the first polymer layer has an opening to expose the device pad. In one embodiment, a redistribution layer (RDL) comprises a landing pad, and the RDL is positioned on the first polymer layer and conductively coupled to the device pad. A second polymer layer is on the RDL, and an under bump metal pad (UBM) is on the landing pad and extends onto a top surface of the second polymer layer. In one embodiment, a shortest distance from a center of the landing pad to an outer edge of the landing pad, and a shortest distance from a center of the UBM to an outer edge of the UBM are in a ratio that ranges from 0.5:1 up to 0.95:1.
摘要翻译：半导体封装包括在衬底上的器件焊盘。第一聚合物层覆盖在基底上，第一聚合物层具有露出装置垫的开口。在一个实施例中，再分配层（RDL）包括着陆焊盘，并且RDL定位在第一聚合物层上并且导电地耦合到器件焊盘。第二聚合物层位于RDL上，下凸块金属垫（UBM）在着陆垫上并延伸到第二聚合物层的顶表面上。在一个实施例中，从着陆焊盘的中心到着陆焊盘的外边缘的最短距离以及从UBM的中心到UBM的外边缘的最短距离的范围为0.5:1 高达0.95：1。

8. 发明授权

US07973418B2 Solder bump interconnect for improved mechanical and thermo-mechanical performance 有权
标题翻译：焊接凸块互连，用于改善机械和热机械性能
公开(公告)号：US07973418B2
公开(公告)日：2011-07-05
申请号：US12107009
申请日：2008-04-21
申请人： Reynante Alvarado , Yuan Lu , Richard Redburn
发明人： Reynante Alvarado , Yuan Lu , Richard Redburn
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L23/3171 , H01L23/3192 , H01L24/02 , H01L24/03 , H01L24/13 , H01L2224/0235 , H01L2224/0239 , H01L2224/0345 , H01L2224/0346 , H01L2224/0401 , H01L2224/04042 , H01L2224/05022 , H01L2224/05073 , H01L2224/05124 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05541 , H01L2224/05548 , H01L2224/05554 , H01L2224/05555 , H01L2224/05567 , H01L2224/05572 , H01L2224/0558 , H01L2224/05644 , H01L2224/05647 , H01L2224/05666 , H01L2224/1148 , H01L2224/13006 , H01L2224/13007 , H01L2224/13021 , H01L2224/13022 , H01L2224/131 , H01L2224/45144 , H01L2224/45147 , H01L2224/48644 , H01L2224/48647 , H01L2224/48666 , H01L2224/48844 , H01L2224/48847 , H01L2224/48866 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/12044 , H01L2924/14 , H01L2924/3011 , H01L2924/351 , H01L2924/00014 , H01L2924/00015 , H01L2224/13099 , H01L2924/00
摘要： An apparatus and method for a semiconductor package including a bump on input-output (IO) structure are disclosed involving a device pad, an under bump metal pad (UBM), a polymer, and a passivation layer. The shortest distance from the center of the device pad to its outer edge, and the shortest distance from the center of the UBM to its outer edge are in a ratio from 0.5:1 to 0.95:1. Also, the shortest distance from the center of the polymer to its outer edge, and the shortest distance from the center of the UBM to its outer edge are in a ratio from 0.35:1 to 0.85:1. Additionally, the shortest distance from the center of the passivation layer to its outer edge, and the shortest distance from the center of the UBM to its outer edge are in a ratio from 0.35:1 to 0.80:1.
摘要翻译：公开了一种用于包括输入 - 输出（IO）结构上的凸块的半导体封装的装置和方法，其涉及器件焊盘，下凸块金属焊盘（UBM），聚合物和钝化层。从装置衬垫的中心到其外边缘的最短距离以及从UBM的中心到其外边缘的最短距离的比例为0.5:1至0.95:1。此外，从聚合物的中心到其外边缘的最短距离以及从UBM的中心到其外边缘的最短距离的比例为0.35:1至0.85:1。此外，从钝化层的中心到其外边缘的最短距离以及从UBM的中心到其外边缘的最短距离的比例为0.35:1至0.80:1。

9. 发明授权

US09070747B2 Electroplating using dielectric bridges 有权
标题翻译：使用介质桥电镀
公开(公告)号：US09070747B2
公开(公告)日：2015-06-30
申请号：US14039384
申请日：2013-09-27
申请人： FlipChip International, LLC
发明人： Eugene A. Stout , Douglas M. Scott , Anthony P. Curtis , Theodore G. Tessier , Guy F. Burgess
IPC分类号： H01L23/544 , H01L21/768 , H01L21/78 , H01L23/31
CPC分类号： H01L21/76837 , C25D5/022 , C25D7/123 , H01L21/76873 , H01L21/78 , H01L23/3171 , H01L23/3192 , H01L24/03 , H01L24/11 , H01L2224/034 , H01L2224/0401 , H01L2224/11462 , H01L2924/12042 , H01L2924/00014 , H01L2924/00
摘要： Structures and methods provide a dielectric bridge for use in electroplating. A method comprises: providing a semiconductor wafer with a plurality of die, wherein a first die is adjacent to a second die, and the first die and second die are separated by a dicing street area; forming a patterned dielectric layer overlying the semiconductor wafer, the dielectric layer including a dielectric bridge that crosses the dicing street area; forming a conductive layer (e.g., a metal seed layer) overlying the dielectric layer, wherein a portion of the conductive layer is overlying the dielectric bridge to provide a current pathway from the first die to the second die; and electroplating targeted areas of the conductive layer by providing current to the second die using the current pathway. Other such bridges formed from the dielectric layer provide current pathways to other die on the wafer.
摘要翻译：结构和方法提供用于电镀的介电桥。一种方法包括：提供具有多个裸片的半导体晶片，其中第一裸片与第二裸片相邻，并且第一裸片和第二裸片由切割街道区域分开; 形成覆盖所述半导体晶片的图案化电介质层，所述电介质层包括穿过所述切割街道区域的电介质桥; 形成覆盖所述电介质层的导电层（例如，金属种子层），其中所述导电层的一部分覆盖在所述电介质桥上，以提供从所述第一管芯到所述第二管芯的电流通路; 以及通过使用电流路径向第二管芯提供电流来电镀导电层的目标区域。由电介质层形成的其它这样的桥提供电流通向晶片上的其它晶粒。

10. 发明授权

US08754524B2 Wafer-level interconnect for high mechanical reliability applications 有权
标题翻译：晶圆级互连，用于高机械可靠性应用
公开(公告)号：US08754524B2
公开(公告)日：2014-06-17
申请号：US13397876
申请日：2012-02-16
申请人： Anthony Curtis , Guy F. Burgess , Michael Johnson , Ted Tessier , Yuan Lu
发明人： Anthony Curtis , Guy F. Burgess , Michael Johnson , Ted Tessier , Yuan Lu
IPC分类号： H01L23/48
CPC分类号： H01L24/10 , B23K35/262 , B23K2101/36 , C22C13/00 , H01L24/13 , H01L2224/0401 , H01L2224/05124 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05171 , H01L2224/0558 , H01L2224/05644 , H01L2224/05647 , H01L2224/13 , H01L2224/131 , H01L2224/16 , H01L2924/00013 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H05K3/3463 , H01L2224/13099 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： An interconnect structure comprises a solder including nickel (Ni) in a range of 0.01 to 0.20 percent by weight. The interconnect structure further includes an intermetallic compound (IMC) layer in contact with the solder. The IMC layer comprises a compound of copper and nickel.
摘要翻译：互连结构包括包含0.01至0.20重量％范围内的镍（Ni）的焊料。互连结构还包括与焊料接触的金属间化合物（IMC）层。 IMC层包含铜和镍的化合物。

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