专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130241070A1 OVERLAPPING CONTACTS FOR SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件的重叠接触
公开(公告)号：US20130241070A1
公开(公告)日：2013-09-19
申请号：US13875443
申请日：2013-05-02
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDARIES INC. , STMICROELECTRONICS, INC.
发明人： Brett H. Engel , Lindsey Hall , David F. Hilscher , Randolph F. Knarr , Steven R. Soss , Jin Z. Wallner
IPC分类号： H01L23/528
CPC分类号： H01L23/528 , H01L21/76816 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device with overlapping contacts is provided. In one aspect, the semiconductor device includes a dielectric layer; a first contact located in the dielectric layer; and a second contact located in the dielectric layer adjacent to the first contact, wherein a portion of the second contact overlaps a top surface of the first contact.
摘要翻译：提供具有重叠触点的半导体器件。在一个方面，半导体器件包括电介质层; 位于介电层中的第一触点; 以及位于所述电介质层中与所述第一触点相邻的第二触点，其中所述第二触点的一部分与所述第一触点的顶表面重叠。

2. 发明授权

US10374106B2 Integrated graphene detectors with waveguides 有权
公开(公告)号：US10374106B2
公开(公告)日：2019-08-06
申请号：US15486849
申请日：2017-04-13
申请人： GLOBALFOUNDRIES INC.
发明人： Ajey P. Jacob
IPC分类号： G02B6/12 , H01L31/18 , H01L27/144 , H01L31/105 , H01L31/0232 , H01L31/0352 , H01L31/0392
摘要： The present disclosure relates to semiconductor structures and, more particularly, to graphene detectors integrated with optical waveguide structures and methods of manufacture. The structure includes a plurality of non-planar fin structures composed of substrate material, and a non-planar sheet of graphene material extending entirely over each of the plurality of non-planar fin structures.

3. 发明授权

US10242867B2 Gate pickup method using metal selectivity 有权
公开(公告)号：US10242867B2
公开(公告)日：2019-03-26
申请号：US15598393
申请日：2017-05-18
申请人： GLOBALFOUNDRIES INC.
发明人： Guillaume Bouche , Vimal Kamineni
IPC分类号： H01L21/02 , H01L29/78 , H01L21/28 , H01L29/49
摘要： A method of fabricating a FinFET device includes forming contact openings for source/drain contacts prior to performing a replacement metal gate (RMG) module. Etch selective metals are used to form source/drain contacts and gate contacts optionally within active device regions using a block and recess technique.

4. 发明授权

US10460782B1 Integrated circuits having single state memory reference cells and methods for operating the same 有权
公开(公告)号：US10460782B1
公开(公告)日：2019-10-29
申请号：US16055952
申请日：2018-08-06
申请人： GLOBALFOUNDRIES, Inc.
发明人： Yentsai Huang
IPC分类号： G11C11/00 , G11C11/16 , G06F11/07 , G11C13/00
摘要： Integrated circuits including memory cells and methods for operating memory cells are provided. In an embodiment, a method is provided for operating a memory including a plurality of operational memory cells. The method includes providing a word line voltage on a selected word line corresponding to a selected operational memory cell of the plurality of operational memory cells and to a corresponding reference memory cell. The method includes applying an operational bias current on an operational bit line to the selected operational memory cell. Also, the method includes scanning a reference bias current from a first value to a second value on a reference bit line to the reference memory cell. Further, the method includes comparing reference cell currents on the reference bit line with an operational cell current on the operational bit line to determine a logic state of the selected operational memory cell.

5. 发明授权

US10382049B1 On-chip calibration circuit and method with half-step resolution 有权
公开(公告)号：US10382049B1
公开(公告)日：2019-08-13
申请号：US16122993
申请日：2018-09-06
申请人： GLOBALFOUNDRIES INC.
发明人： Eric Hunt-Schroeder , John A. Fifield
IPC分类号： H03M1/10 , G01R35/00 , H03M1/66 , H03M1/06
摘要： Disclosed is a calibration circuit and method. The circuit includes: a DAC that outputs an analog parameter and includes output parameter adjustment circuitry; a comparator that receives a reference parameter and the analog parameter; and a control circuit (with select logic) connected to the comparator and DAC in a feedback loop. During a calibration mode, the magnitude of the analog parameter is adjusted by ½ DAC step in one direction and the feedback loop is used to perform a binary search calibration process. During an operation mode, the magnitude of the analog parameter is adjusted by ½ DAC step in the opposite direction. The select logic selects the DAC step identified by the calibration process or the next higher DAC step as a final DAC step. The control circuit outputs a final DAC code corresponding to the final DAC step and the DAC generates a calibrated parameter based thereon.

6. 发明授权

US09530654B2 FINFET fin height control 有权
标题翻译： FINFET翅片高度控制
公开(公告)号：US09530654B2
公开(公告)日：2016-12-27
申请号：US13862819
申请日：2013-04-15
申请人： GLOBALFOUNDRIES Inc.
发明人： Nicholas V. Licausi
IPC分类号： H01L21/308 , H01L21/306 , H01L27/088 , H01L29/66 , H01L21/8234 , H01L21/762 , H01L21/3105
CPC分类号： H01L21/30625 , H01L21/3105 , H01L21/762 , H01L21/823431 , H01L27/0886 , H01L29/66795
摘要： Fin height control techniques for FINFET fabrication are disclosed. The technique includes a method for controlling the height of plurality of fin structures to achieve uniform height thereof relative to a top surface of isolation material located between fin structures on a semiconductor substrate. The isolation material located between fin structures may be selectively removed after treatment to increase its mechanical strength such as by, for example, annealing and curing. A sacrificial material may be deposited over the isolation material between the fin structures in a substantially uniform thickness. The top portion of the fin structures may be selectively removed to achieve a uniform planar surface over the fin structures and sacrificial material. The sacrificial material may then be selectively removed to achieve a uniform fin height relative to the isolation material.
摘要翻译：公开了FinFET制造的翅片高度控制技术。该技术包括一种用于控制多个翅片结构的高度以实现其相对于位于半导体衬底上的翅片结构之间的隔离材料的顶表面的均匀高度的方法。位于翅片结构之间的隔离材料可以在处理之后选择性地除去以增加其机械强度，例如通过退火和固化。牺牲材料可以以基本均匀的厚度沉积在翅片结构之间的隔离材料上。可以选择性地去除翅片结构的顶部以在翅片结构和牺牲材料上实现均匀的平坦表面。然后可以选择性地去除牺牲材料以实现相对于隔离材料的均匀的翅片高度。

7. 发明授权

US08293606B2 Body tie test structure for accurate body effect measurement 有权
标题翻译：身体绑带测试结构，用于精确的身体效应测量
公开(公告)号：US08293606B2
公开(公告)日：2012-10-23
申请号：US12973377
申请日：2010-12-20
申请人： Sriram Madhavan , Qiang Chen , Darin A. Chan , Jung-Suk Goo
发明人： Sriram Madhavan , Qiang Chen , Darin A. Chan , Jung-Suk Goo
IPC分类号： H01L27/12
CPC分类号： H01L29/78615 , H01L22/34
摘要： A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.
摘要翻译：提供了一种身体搭接测试结构及其制造方法。晶体管包括形成在半导体材料层中的主体结合半导体绝缘体（SOI）晶体管，该晶体管包括具有基本恒定的栅极长度L的十字形栅极结构。绝缘阻挡层能够形成间隔区域所述半导体材料层将所述源极和漏极区域与所述主体连接区域分开。具有与本征晶体管主体基本上相同的反转特性的导电沟道通过间隔区将主体连接到本征晶体管本体。

8. 发明授权

US10381354B2 Contact structures and methods of making the contact structures 有权
公开(公告)号：US10381354B2
公开(公告)日：2019-08-13
申请号：US15861161
申请日：2018-01-03
申请人： GLOBALFOUNDRIES Inc.
发明人： Daniel Chanemougame , Emilie Bourjot
IPC分类号： H01L27/11 , H01L29/78 , H01L23/522 , H01L23/528 , H01L29/417
摘要： One illustrative IC product disclosed herein includes a first merged doped source/drain region that includes first and second doped regions and an isolation structure positioned adjacent the first doped region. In this example, the product also includes a contact structure positioned adjacent the isolation structure, wherein the contact structure includes a first portion positioned below an upper surface of the first merged doped source/drain region and a second portion positioned above the upper surface, wherein the first portion physically contacts both the first and second doped regions. The product also includes a layer of insulating material positioned on and in physical contact with a portion of an upper surface of the first portion of the contact structure.

9. 发明授权

US10332803B1 Hybrid gate-all-around (GAA) field effect transistor (FET) structure and method of forming 有权
公开(公告)号：US10332803B1
公开(公告)日：2019-06-25
申请号：US15973817
申请日：2018-05-08
申请人： GLOBALFOUNDRIES INC.
发明人： Ruilong Xie , Edward J. Nowak , Bipul C. Paul , Steven R. Soss , Julien Frougier , Daniel Chanemougame , Lars W. Liebmann
IPC分类号： H01L21/8238 , H01L21/02 , H01L29/06 , H01L29/423 , H01L29/49 , H01L29/786 , H01L29/66 , H01L21/3065 , H01L21/308 , H01L27/092
摘要： Various embodiments relate to gate-all-around (GAA) transistors and methods of forming such transistors. In some embodiments, a method performed on a precursor structure includes selectively removing a sacrificial nanosheet to open a vertical gap between a pair of semiconductor nanosheets; forming a first work function metal to surround the precursor nanosheet stack and fin, the first work function metal filling the vertical gap between the pair of semiconductor nano sheets; selectively removing first work function metal surrounding the fin while preserving an entirety of first work function metal surrounding the nanosheet stack; and forming a second work function metal: over a remaining portion of the first work function metal on nanosheet stack, and surrounding the fin, where first work function metal includes a different material than second work function metal.

10. 发明授权

US10236768B2 Switched-capacitor charge pump with reduced diode threshold voltage and on state resistance 有权
公开(公告)号：US10236768B2
公开(公告)日：2019-03-19
申请号：US15599596
申请日：2017-05-19
申请人： GLOBALFOUNDRIES INC.
发明人： Wern Ming Koe
IPC分类号： G05F1/10 , G05F3/02 , H02M3/07 , H03K5/1532
摘要： The present disclosure relates to a structure which includes a diode-based Dickson charge pump which is configured to use an independent multi-gate device to reduce a threshold voltage of a plurality of transistor diodes during a charging and pumping phase.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式