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1. 发明授权

US09607967B1 Multi-chip semiconductor package with via components and method for manufacturing the same 有权
公开(公告)号：US09607967B1
公开(公告)日：2017-03-28
申请号：US14977645
申请日：2015-12-22
申请人： INOTERA MEMORIES, INC.
发明人： Shing-Yih Shih
IPC分类号： H01L25/065 , H01L23/552 , H01L23/31 , H01L23/00
CPC分类号： H01L25/0657 , H01L21/561 , H01L21/568 , H01L23/3157 , H01L23/552 , H01L24/02 , H01L24/97 , H01L2224/02372 , H01L2224/0401 , H01L2224/131 , H01L2224/13147 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81005 , H01L2224/81192 , H01L2224/81193 , H01L2224/83005 , H01L2224/92125 , H01L2224/97 , H01L2225/0652 , H01L2225/06537 , H01L2225/06544 , H01L2924/1432 , H01L2924/1433 , H01L2924/1434 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/18161 , H01L2924/19105 , H01L2924/3025 , H01L2924/3511 , H01L2924/014 , H01L2924/00014 , H01L2224/81 , H01L2224/83
摘要： A multi-chip semiconductor package includes a lower RDL interposer, a first chip on the lower RDL interposer within a chip mounting area, via components mounted within a peripheral area, and a first molding compound surrounding the first chip and the via components. Each of the via components comprises a substrate portion and a connection portion coupled to the substrate portion. An upper RDL interposer is integrally constructed on the first chip, on the via components, and on the first molding compound. The upper RDL interposer is electrically connected to the connection portion of each of the via components. A second chip is mounted on the upper RDL interposer. A second molding compound surrounds the second chip.

2. 发明授权

US09576933B1 Fan-out wafer level packaging and manufacturing method thereof 有权
标题翻译：扇形晶圆级封装及制造方法
公开(公告)号：US09576933B1
公开(公告)日：2017-02-21
申请号：US14989782
申请日：2016-01-06
申请人： INOTERA MEMORIES, INC.
发明人： Yi-Jen Lo
IPC分类号： H01L23/48 , H01L25/065 , H01L23/31 , H01L23/485 , H01L23/00 , H01L49/02
CPC分类号： H01L25/0655 , H01L21/561 , H01L21/568 , H01L23/295 , H01L23/481 , H01L23/485 , H01L24/19 , H01L24/20 , H01L28/75 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/24137 , H01L2224/92125 , H01L2224/92144 , H01L2224/97 , H01L2924/15311 , H01L2924/18161 , H01L2924/18162 , H01L2224/83005
摘要： A fan-out wafer-level-package (FOWLP) is provided. The FOWLP includes a redistribution layer (RDL) comprising a dielectric layer and a first metal layer; a passive device in the first metal layer; a first passivation layer covering a top surface of the RDL; a second passivation layer covering a bottom surface of the RDL; a chip mounted on the first passivation layer; a molding compound around the chip and on the first passivation layer; a via opening penetrating through the second passivation layer, the dielectric layer, and the second passivation layer, thereby exposing a terminal of the chip; a contact opening in the second passivation layer; and a second metal layer in the via opening and the contact opening to electrically connect one electrode of the passive device with the terminal of the chip.
摘要翻译：提供扇形晶圆级封装（FOWLP）。 FOWLP包括包含电介质层和第一金属层的再分布层（RDL）; 第一金属层中的无源器件; 覆盖RDL的顶表面的第一钝化层; 覆盖RDL的底表面的第二钝化层; 安装在所述第一钝化层上的芯片; 围绕芯片和第一钝化层的模塑料; 穿过所述第二钝化层，所述介电层和所述第二钝化层的通孔，从而使所述芯片的端子露出; 在第二钝化层中的接触开口; 以及通孔开口中的第二金属层和接触开口，以将无源器件的一个电极与芯片的端子电连接。

3. 发明授权

US09576931B1 Method for fabricating wafer level package 有权
标题翻译：制造晶圆级封装的方法
公开(公告)号：US09576931B1
公开(公告)日：2017-02-21
申请号：US15047632
申请日：2016-02-19
申请人： INOTERA MEMORIES, INC.
发明人： Shing-Yih Shih
IPC分类号： B65D85/00 , H01L33/48 , H01L23/00 , H01L21/56 , H01L21/683 , H01L21/3105 , H01L21/78
CPC分类号： H01L24/96 , H01L21/31053 , H01L21/561 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/78 , H01L23/3114 , H01L24/11 , H01L24/16 , H01L24/73 , H01L24/81 , H01L24/92 , H01L24/97 , H01L2221/68327 , H01L2221/68359 , H01L2221/68381 , H01L2224/0231 , H01L2224/13024 , H01L2224/16225 , H01L2224/2919 , H01L2224/73204 , H01L2224/81001 , H01L2224/81192 , H01L2224/81815 , H01L2224/92125 , H01L2924/00014 , H01L2924/15174 , H01L2924/181 , H01L2924/18161 , H01L2924/00012 , H01L2224/13099
摘要： A method for fabricating a wafer level package is disclosed. A carrier is provided. A redistributed layer (RDL) layer is formed on the carrier. Semiconductor dies are mounted on the RDL layer. The semiconductor dies are molded with a molding compound, thereby forming a molded wafer. A grinding process is then performed to remove a central portion of the molding compound, thereby forming a recess and an outer peripheral ring portion surrounding the recess. The carrier is then removed to expose a lower surface of the RDL layer. Solder bumps or solder balls are formed on the lower surface of the RDL layer.
摘要翻译：公开了一种制造晶片级封装的方法。提供载体。在载体上形成再分布层（RDL）层。半导体管芯安装在RDL层上。用模塑料模制半导体管芯，从而形成模制的晶片。然后进行研磨处理以除去模制化合物的中心部分，从而形成凹部和围绕凹部的外周环部分。然后移除载体以暴露RDL层的下表面。在RDL层的下表面上形成焊锡凸块或焊球。

4. 发明授权

US09496358B2 Semiconductor device and fabrication method therefor 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US09496358B2
公开(公告)日：2016-11-15
申请号：US14289936
申请日：2014-05-29
申请人： INOTERA MEMORIES, INC.
发明人： Tzung-Han Lee , Yaw-Wen Hu , Neng-Tai Shih , Heng Hao Hsu , Yu Jing Chang , Hsu Chiang
IPC分类号： H01L29/423 , H01L21/265 , H01L29/66 , H01L29/78
CPC分类号： H01L29/4236 , H01L21/26586 , H01L29/66621 , H01L29/7834
摘要： A semiconductor electronic device structure includes a substrate having a trench disposed therein, a gate electrode disposed in the trench, and a gate dielectric layer disposed on the surface in the trench. The substrate and the gate electrode are electrically insulated from each other by the gate dielectric layer. The substrate further has a pair of doped areas. The doped areas each are vertically disposed along the two respective lateral sides of the trench. The doped areas each have a first portion and a second portion arranged atop the first portion. The first portion extends vertically to the portion of the substrate that is aligned to the gate electrode. The lateral dimension of the first portion is smaller than the lateral dimension of the second portion, and the doping concentration of the first portion is lighter than the doping concentration of the second portion.
摘要翻译：半导体电子器件结构包括其中设置有沟槽的衬底，设置在沟槽中的栅电极和设置在沟槽中的表面上的栅极电介质层。基板和栅电极通过栅介质层彼此电绝缘。衬底还具有一对掺杂区域。掺杂区域各自沿沟槽的两个相应横向侧面垂直设置。掺杂区域各自具有布置在第一部分顶部的第一部分和第二部分。第一部分垂直延伸到与栅电极对准的衬底部分。第一部分的横向尺寸小于第二部分的横向尺寸，并且第一部分的掺杂浓度比第二部分的掺杂浓度轻。

5. 发明授权

US09401326B1 Split contact structure and fabrication method thereof 有权
标题翻译：分离接触结构及其制造方法
公开(公告)号：US09401326B1
公开(公告)日：2016-07-26
申请号：US14720830
申请日：2015-05-24
申请人： INOTERA MEMORIES, INC.
发明人： Cheng-Yeh Hsu , Hsin-Pin Huang , Chih-Hao Cheng
IPC分类号： H01L21/8242 , H01L23/528 , H01L23/532 , H01L27/108
CPC分类号： H01L27/10844 , H01L27/10808 , H01L27/10855 , H01L27/10882
摘要： A split contact structure includes a semiconductor substrate having a major surface; a first upwardly protruding structure disposed on the major surface; a first cell contact region in the major surface and being close to the first upwardly protruding structure; a second upwardly protruding structure disposed on the major surface; a second cell contact region in the major surface and being close to the second upwardly protruding structure; a first patterned layer stacked on the first upwardly protruding structure; a second patterned layer stacked on the first upwardly protruding structure; a first contact structure disposed on a sidewall of the first upwardly protruding structure and being in direct contact with the first cell contact region; and a second contact structure disposed on a sidewall of the second upwardly protruding structure and being in direct contact with the second cell contact region.
摘要翻译：分割接触结构包括具有主表面的半导体衬底; 设置在主表面上的第一向上突出的结构; 主表面中的第一细胞接触区域并且靠近第一向上突出结构; 设置在主表面上的第二向上突出的结构; 在主表面中的第二细胞接触区域并且靠近第二向上突出的结构; 堆叠在第一向上突出结构上的第一图案层; 堆叠在第一向上突出结构上的第二图案层; 第一接触结构，其设置在所述第一向上突出结构的侧壁上并与所述第一电池接触区域直接接触; 以及第二接触结构，其设置在所述第二向上突出结构的侧壁上并与所述第二电池接触区域直接接触。

6. 发明申请

US20150243597A1 SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING WARPING 审中-公开
标题翻译：能够抑制加热的半导体器件
公开(公告)号：US20150243597A1
公开(公告)日：2015-08-27
申请号：US14190025
申请日：2014-02-25
申请人： INOTERA MEMORIES, INC.
发明人： Hsu Chiang , Yaw-Wen Hu
IPC分类号： H01L23/528 , H01L23/00 , H01L23/31 , H01L23/29 , H01L23/498 , B81B7/00
CPC分类号： H01L23/291 , H01L23/3171 , H01L23/522 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate having a front side and a rear side, a plurality of dielectric layers on the front side, a plurality of interconnection circuit structures in the dielectric layers, and at least one backside passivation layer on the rear side. The backside passivation layer and the top passivation layer are made of the same material and have substantially the same thickness.
摘要翻译：半导体器件包括具有前侧和后侧的衬底，前侧上的多个电介质层，电介质层中的多个互连电路结构以及后侧的至少一个后侧钝化层。背面钝化层和顶部钝化层由相同的材料制成并具有基本上相同的厚度。

7. 发明申请

US20150214233A1 MANUFACTURING METHOD OF CAPACITOR LOWER ELECTRODE AND SEMICONDUCTOR STORAGE DEVICE USING THE SAME 有权
标题翻译：电容器下电极的制造方法及使用其的半导体存储器件
公开(公告)号：US20150214233A1
公开(公告)日：2015-07-30
申请号：US14251792
申请日：2014-04-14
申请人： INOTERA MEMORIES, INC.
发明人： REGAN STANLEY TSUI , TZUNG-HAN LEE
IPC分类号： H01L27/108 , H01L49/02
CPC分类号： H01L27/10844 , H01L27/0805 , H01L27/101 , H01L27/108 , H01L27/10814 , H01L27/10852 , H01L28/40 , H01L28/60 , H01L28/91
摘要： A manufacturing method of capacitor lower electrode of the instant disclosure comprises the steps of: providing a semiconductor substrate; forming a sacrificial laminate on the semiconductor substrate; forming a plurality of capacitor trenches in the sacrificial laminate; forming a plurality of lower electrode structures in the capacitor trenches respectively; etching back the sacrificial laminate to a desired thickness to expose an upper portion of each of the lower electrode structures; forming a liner layer to conformally cover the sacrificial laminate and the upper portions of the lower electrode structures; patterning the liner layer to form an insulating spacer on the sidewalls of each of the upper portions, wherein two adjacent insulating spacers are configured to have a self-aligned opening positioned therebetween; and performing a wet-etching process to remove the sacrificial laminate through the self-aligned openings.
摘要翻译：本公开的电容器下电极的制造方法包括以下步骤：提供半导体衬底; 在所述半导体衬底上形成牺牲层压体; 在所述牺牲层叠体中形成多个电容器沟槽; 在电容器沟槽中分别形成多个下电极结构; 将牺牲层压板刻蚀成所需的厚度以暴露每个下电极结构的上部; 形成衬层以保形地覆盖牺牲层压板和下电极结构的上部; 图案化衬垫层以在每个上部的侧壁上形成绝缘间隔件，其中两个相邻的绝缘间隔件构造成具有位于其间的自对准开口; 并进行湿蚀刻工艺以通过自对准开口去除牺牲层压体。

8. 发明申请

US20140306731A1 METHOD OF TESTING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR TESTING SYSTEM 审中-公开
标题翻译：测试半导体器件和半导体测试系统的方法
公开(公告)号：US20140306731A1
公开(公告)日：2014-10-16
申请号：US13949407
申请日：2013-07-24
申请人： INOTERA MEMORIES, INC.
发明人： WEI-CHIH WANG
IPC分类号： G01R31/26 , G01Q60/30
CPC分类号： G01Q60/30 , G01R31/311
摘要： A method of testing semiconductor devices is provided includes: exposing one end of the device contact on the surface of the semiconductor; using a scanning probe microscopy apparatus to scan a diagnostic area on the semiconductor; applying a direct current bias between the conductive probe and a substrate of the semiconductor; directing a testing radiation at the diagnostic area to increase amount of free carriers in the device contacts and in the semiconductor layer under the device contacts; and detecting the current flowing through the conductive probe and the substrate, wherein a defect current signal is measured when the probe is in contact with a defective device contact and a normal current signal is measured when the probe is in contact with a normal device contact, wherein the testing radiation increases the current measured to increase the difference between the defect signal and the normal signal.
摘要翻译：提供一种测试半导体器件的方法，包括：将器件接触的一端暴露在半导体的表面上; 使用扫描探针显微镜装置扫描半导体上的诊断区域; 在导电探针和半导体的衬底之间施加直流偏压; 在诊断区域引导测试辐射以增加器件触点中的自由载流子和器件触点下半导体层中的自由载流子的数量; 并且检测流过导电探针和衬底的电流，其中当探针与缺陷器件接触接触时测量缺陷电流信号，并且当探头与正常器件接触接触时测量正常电流信号，其中测试辐射增加测量的电流以增加缺陷信号与正常信号之间的差异。

9. 发明授权

US08779494B2 High-k metal gate random access memory 有权
标题翻译：高k金属门随机存取存储器
公开(公告)号：US08779494B2
公开(公告)日：2014-07-15
申请号：US13426825
申请日：2012-03-22
申请人： Tzung-Han Lee , Chung-Lin Huang , Ron-Fu Chu
发明人： Tzung-Han Lee , Chung-Lin Huang , Ron-Fu Chu
IPC分类号： H01L29/94
CPC分类号： H01L27/10873 , H01L27/10885 , H01L27/10891
摘要： The instant disclosure relates to a high-k metal gate random access memory. The memory includes a substrate, a plurality of bit line units, source regions, gate structures, drain regions, word line units, and capacitance units. The substrate has a plurality of trenches, and the bit line units are arranged on the substrate. The source regions are disposed on the bit line units, and the gate structures are disposed on the source regions. Each gate structure has a metal gate and a channel area formed therein. The gate structures are topped with the drain regions. The word lines units are arranged between the source and drain regions. The capacitance units are disposed on the drain regions. Another memory is also disclosed, where each drain region and a portion of each gate structure are disposed in the respective capacitance unit, with the drain region being a lower electrode layer.
摘要翻译：本公开涉及高k金属栅极随机存取存储器。存储器包括衬底，多个位线单元，源极区，栅极结构，漏极区，字线单元和电容单元。衬底具有多个沟槽，并且位线单元布置在衬底上。源极区域设置在位线单元上，栅极结构设置在源极区域上。每个栅极结构具有形成在其中的金属栅极和沟道区域。栅极结构顶部带有漏极区域。字线单元布置在源区和漏区之间。电容单元设置在漏极区域上。还公开了另一种存储器，其中每个漏极区域和每个栅极结构的一部分设置在相应的电容单元中，漏极区域是下部电极层。

10. 发明授权

US08753061B2 Transport system having multilayer tracks and controlling method thereof 有权
标题翻译：具有多层轨道的运输系统及其控制方法
公开(公告)号：US08753061B2
公开(公告)日：2014-06-17
申请号：US13013061
申请日：2011-01-25
申请人： Chao-Hsiang Tseng , Huei-Lan Kuo
发明人： Chao-Hsiang Tseng , Huei-Lan Kuo
IPC分类号： B61B3/02
CPC分类号： H01L21/67766
摘要： A transport system having multilayer tracks is presented. The system has a bottom track and at least one top track disposed above on the bottom track. Shuttle carriages are moving along the top and bottom tracks. The shuttle body of each shuttle carriage has a first locking portion on the top end thereof, and has a second locking portion on the bottom end thereof. The second locking portion of the shuttle carriage on the top track can be locked with the first locking portion of the shuttle carriage on the bottom track. Therefore, the two transports on different tracks are locked so that the object can be transported between the top and bottom tracks.
摘要翻译：提出了一种具有多层轨迹的运输系统。该系统具有底部轨道和设置在底部轨道上方的至少一个顶部轨道。穿梭车沿着顶部和底部轨道移动。每个梭车的梭体具有在其顶端上的第一锁定部分，并且在其底端上具有第二锁定部分。梭子滑架在顶部轨道上的第二锁定部分可以与梭车的第一锁定部分锁定在底部轨道上。因此，不同轨道上的两个传送器被锁定，使得物体可以在顶部和底部轨道之间传送。

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