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1. 发明授权

US08009483B2 Nonvolatile memory cell and data latch incorporating nonvolatile memory cell 有权
标题翻译：非易失性存储单元和包含非易失性存储单元的数据锁存器
公开(公告)号：US08009483B2
公开(公告)日：2011-08-30
申请号：US12425937
申请日：2009-04-17
申请人： Masaaki Kamiya
发明人： Masaaki Kamiya
IPC分类号： G11C16/04
CPC分类号： G11C16/0441
摘要： A nonvolatile memory cell includes: a first NMOS transistor having a floating gate; a second NMOS transistor and a third NMOS transistor connected to a drain side and a source side of the first NMOS transistor; and a first PMOS transistor and a second PMOS transistor each having the floating gate as a gate, and wherein a read signal is inputted to gates of the second and third NMOS transistors, a control gate signal is inputted to a source and an n-well of the first PMOS transistor, an erase signal is inputted to a source and an n-well of the second PMOS transistor, and a write data signal is inputted to a source of the first NMOS transistor.
摘要翻译：非易失性存储单元包括：具有浮置栅极的第一NMOS晶体管; 连接到第一NMOS晶体管的漏极侧和源极侧的第二NMOS晶体管和第三NMOS晶体管; 以及分别具有浮置栅极作为栅极的第一PMOS晶体管和第二PMOS晶体管，并且其中读取信号被输入到第二和第三NMOS晶体管的栅极，控制栅极信号被输入到源极和n阱第一PMOS晶体管的漏极信号被输入到第二PMOS晶体管的源极和n阱，写入数据信号被输入到第一NMOS晶体管的源极。

2. 发明授权

US09847433B2 Integrated MOS varicap, and voltage controlled oscillator and filter having same 有权
公开(公告)号：US09847433B2
公开(公告)日：2017-12-19
申请号：US15314712
申请日：2015-05-11
申请人： Interchip Corporation
发明人： Masaaki Kamiya , Ryuji Ariyoshi
IPC分类号： H01L29/93 , H01L27/08 , H03B5/36 , H03H11/04
CPC分类号： H01L29/93 , H01L27/0808 , H01L28/00 , H03B5/366 , H03B5/368 , H03B2201/0208 , H03H11/04
摘要： Each of varicaps 50A to 50C configured to be connected in parallel is an MOS capacitor III produced under a common and single process condition. Each of the varicaps 50A to 50C has a conductor layer serving as a second electrode and formed via a capacitance insulating film on a first conductivity-type semiconductor substrate serving as a first electrode, and a second conductivity-type impurity region formed near a surface in proximity to a region of the first conductivity-type semiconductor substrate opposing the conductor layer. Each of the varicaps 50A to 50C is configured such that a capacitance value as a capacitance element between the first conductivity-type semiconductor substrate serving as the first electrode and the conductor layer serving as the second electrode is changed by applying a control voltage to the conductor layer while applying any one of a plurality of types of direct-current voltages having different voltages to the second conductivity-type impurity region.

3. 发明授权

US07515001B2 AC amplifier and piezoelectric vibrator oscillator 失效
标题翻译：交流放大器和压电振子振荡器
公开(公告)号：US07515001B2
公开(公告)日：2009-04-07
申请号：US11517024
申请日：2006-09-07
申请人： Masaaki Kamiya
发明人： Masaaki Kamiya
IPC分类号： H03G3/30
CPC分类号： H03B5/32 , H03B5/364 , H03F1/0216 , H03F3/3022 , H03F11/00
摘要： An AC amplifier has an amplification circuit, and a bias circuit connected together by connecting wiring. The bias circuit receives an input of an AC signal from the amplification circuit via the connecting wiring. A DC voltage of the bias circuit conformed to the amplitude of the AC signal of the amplification circuit is supplied to the amplification circuit via the connecting wiring.
摘要翻译：交流放大器具有放大电路和偏置电路，通过连接布线连接在一起。偏置电路经由连接布线从放大电路接收AC信号的输入。与放大电路的交流信号的振幅一致的偏置电路的直流电压通过连接配线供给放大电路。

4. 发明申请

US20090262584A1 Nonvolatile Memory Cell and Data Latch Incorporating Nonvolatile Memory Cell 有权
标题翻译：非易失性存储器单元和数据锁存器结合非易失性存储器单元
公开(公告)号：US20090262584A1
公开(公告)日：2009-10-22
申请号：US12425937
申请日：2009-04-17
申请人： Masaaki Kamiya
发明人： Masaaki Kamiya
IPC分类号： G11C16/04 , G11C7/10
CPC分类号： G11C16/0441
摘要： A nonvolatile memory cell, comprising: a first NMOS transistor having a floating gate; a second NMOS transistor and a third NMOS transistor connected to a drain side and a source side of the first NMOS transistor; and a first PMOS transistor and a second PMOS transistor each having the floating gate as a gate, and wherein a read signal is inputted to gates of the second and third NMOS transistors, a control gate signal is inputted to a source and an n-well of the first PMOS transistor, an erase signal is inputted to a source and an n-well of the second PMOS transistor, and a write data signal is inputted to a source of the first NMOS transistor.
摘要翻译：一种非易失性存储单元，包括：具有浮置栅极的第一NMOS晶体管; 连接到第一NMOS晶体管的漏极侧和源极侧的第二NMOS晶体管和第三NMOS晶体管; 以及分别具有浮置栅极作为栅极的第一PMOS晶体管和第二PMOS晶体管，并且其中读取信号被输入到第二和第三NMOS晶体管的栅极，控制栅极信号被输入到源极和n阱第一PMOS晶体管的漏极信号被输入到第二PMOS晶体管的源极和n阱，写入数据信号被输入到第一NMOS晶体管的源极。

5. 发明申请

US20060255871A1 Inverting amplifier and crystal oscillator having same 失效
标题翻译：反相放大器和晶振相同
公开(公告)号：US20060255871A1
公开(公告)日：2006-11-16
申请号：US11430952
申请日：2006-05-10
申请人： Masaaki Kamiya
发明人： Masaaki Kamiya
IPC分类号： H03B5/32
CPC分类号： H03B5/368 , H03B5/364 , H03B2200/0012
摘要： A bypass capacitance is connected to a node between first and second self-bias resistances connected in series between an input and an output of an inverter. The bypass capacitance accommodates changes in the output voltage of the inverter to suppress the feedback effect from the output side to the input side of the inverter. That is, the bypass capacitance plays the role of suppressing a decrease in the input impedance by the Miller effect.
摘要翻译：旁路电容连接到在逆变器的输入和输出之间串联连接的第一和第二自偏压之间的节点。旁路电容适应变频器的输出电压的变化，以抑制从逆变器的输出侧到输入侧的反馈效应。也就是说，旁路电容起到通过米勒效应抑制输入阻抗的降低的作用。

6. 发明授权

US07391279B2 Inverting amplifier and crystal oscillator having same 失效
标题翻译：反相放大器和晶振相同
公开(公告)号：US07391279B2
公开(公告)日：2008-06-24
申请号：US11430952
申请日：2006-05-10
申请人： Masaaki Kamiya
发明人： Masaaki Kamiya
IPC分类号： H03B5/32
CPC分类号： H03B5/368 , H03B5/364 , H03B2200/0012
摘要： A bypass capacitance is connected to a node between first and second self-bias resistances connected in series between an input and an output of an inverter. The bypass capacitance accommodates changes in the output voltage of the inverter to suppress the feedback effect from the output side to the input side of the inverter. That is, the bypass capacitance plays the role of suppressing a decrease in the input impedance by the Miller effect.
摘要翻译：旁路电容连接到在逆变器的输入和输出之间串联连接的第一和第二自偏压之间的节点。旁路电容适应变频器的输出电压的变化，以抑制从逆变器的输出侧到输入侧的反馈效应。也就是说，旁路电容起到通过米勒效应抑制输入阻抗的降低的作用。

7. 发明申请

US20170200834A1 Integrated MOS Varicap, and Voltage Controlled Oscillator and Filter Having Same 有权
公开(公告)号：US20170200834A1
公开(公告)日：2017-07-13
申请号：US15314712
申请日：2015-05-11
申请人： Interchip Corporation
发明人： Masaaki Kamiya , Ryuji Ariyoshi
IPC分类号： H01L29/93 , H03B5/36 , H03H11/04 , H01L27/08
CPC分类号： H01L29/93 , H01L27/0808 , H01L28/00 , H03B5/366 , H03B5/368 , H03B2201/0208 , H03H11/04
摘要： Each of varicaps 50A to 50C configured to be connected in parallel is an MOS capacitor III produced under a common and single process condition. Each of the varicaps 50A to 50C has a conductor layer serving as a second electrode and formed via a capacitance insulating film on a first conductivity-type semiconductor substrate serving as a first electrode, and a second conductivity-type impurity region formed near a surface in proximity to a region of the first conductivity-type semiconductor substrate opposing the conductor layer. Each of the varicaps 50A to 50C is configured such that a capacitance value as a capacitance element between the first conductivity-type semiconductor substrate serving as the first electrode and the conductor layer serving as the second electrode is changed by applying a control voltage to the conductor layer while applying any one of a plurality of types of direct-current voltages having different voltages to the second conductivity-type impurity region.

8. 发明申请

US20120274305A1 Voltage Regulator and Voltage-Regulator-Equipped Oscillation Circuit 审中-公开
标题翻译：稳压器和电压调节器配备的振荡电路
公开(公告)号：US20120274305A1
公开(公告)日：2012-11-01
申请号：US13456266
申请日：2012-04-26
申请人： Masaaki Kamiya , Ryuji Ariyoshi
发明人： Masaaki Kamiya , Ryuji Ariyoshi
IPC分类号： G05F3/02
CPC分类号： G05F3/16
摘要： A voltage regulator comprises an N type depletion MOS transistor having a drain connected to the positive electrode side of a power supply, a source connected to a stabilizing capacitor, and a gate receiving a constant reference voltage, and has an output terminal at the source of the N type depletion MOS transistor. In this simple circuit configuration, the voltage regulator can markedly reduce a noise carried on an output voltage.
摘要翻译：电压调节器包括N型耗尽型MOS晶体管，其漏极连接到电源的正极侧，连接到稳定电容器的源极和接收恒定参考电压的栅极，并且具有输出端子 N型耗尽型MOS晶体管。在这种简单的电路配置中，电压调节器可以显着降低输出电压带来的噪声。

9. 发明申请

US20070063768A1 AC amplifier and piezoelectri vibrator oscillator 失效
标题翻译：交流放大器和压电振子振荡器
公开(公告)号：US20070063768A1
公开(公告)日：2007-03-22
申请号：US11517024
申请日：2006-09-07
申请人： Masaaki Kamiya
发明人： Masaaki Kamiya
IPC分类号： H03G3/20
CPC分类号： H03B5/32 , H03B5/364 , H03F1/0216 , H03F3/3022 , H03F11/00
摘要： An AC amplifier has an amplification circuit, and a bias circuit connected together by connecting wiring. The bias circuit receives an input of an AC signal from the amplification circuit via the connecting wiring. A DC voltage of the bias circuit conformed to the amplitude of the AC signal of the amplification circuit is supplied to the amplification circuit via the connecting wiring.
摘要翻译：交流放大器具有放大电路和偏置电路，通过连接布线连接在一起。偏置电路经由连接布线从放大电路接收AC信号的输入。与放大电路的交流信号的振幅一致的偏置电路的直流电压通过连接配线供给放大电路。

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