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    • 3. 发明授权
    • Managing and indentifying multiple memory storage devices
    • 管理和识别多个内存存储设备
    • US08667191B2
    • 2014-03-04
    • US12688792
    • 2010-01-15
    • Choon-Tak TangChin-Tang YenNgoc LeDavid Sun
    • Choon-Tak TangChin-Tang YenNgoc LeDavid Sun
    • G06F13/00G06F13/36G06F13/20
    • G06F13/387G06F3/0679
    • A management hub is disclosed. The management hub comprises an interface; a master hub controller coupled to the interface; a plurality of ports coupled to the master hub controller; a microcontroller coupled to the master hub controller; and hub setting switch and a slave hub controller coupled to the microcontroller and the plurality of ports. The management hub also includes a memory device coupled to the microcontroller, the memory device including a hidden drive information partition and a hidden drive organizer partition for managing and identifying information in various drives coupled to the plurality of ports, wherein when the management hub is first connected to a host system the drives are displayed in an inactive state.
    • 公布了一个管理中心。 管理中心包括一个接口; 耦合到所述接口的主集线器控制器; 耦合到主集线器控制器的多个端口; 耦合到主集线器控制器的微控制器; 和集线器设置开关以及耦合到微控制器和多个端口的从属集线器控制器。 管理集线器还包括耦合到微控制器的存储器设备,该存储器设备包括隐藏的驱动器信息分区和用于管理和识别耦合到多个端口的各种驱动器中的信息的隐藏的驱动器组织器分区,其中当管理集线器第一时 连接到主机系统,驱动器显示为非活动状态。
    • 6. 发明授权
    • Method of fabricating a chip
    • US08445297B2
    • 2013-05-21
    • US12568633
    • 2009-09-28
    • Wei Koh
    • Wei Koh
    • H01L21/66
    • G11C29/00H01L22/14H01L22/20H01L2924/014
    • A method of fabricating a chip may include the step of providing a first electrical part. The method may also include the step of forming a shell with the first electrical part embedded in a first side portion of the shell and a cavity in a second side portion of the shell. The method may include the step of testing the embedded first electrical part to determine whether the first electrical part is defective or functional. The method may also include the steps of providing a second electrical part, inserting the second electrical part within the cavity of the shell second side portion, establishing electrical communication between the first and second electrical parts if a test result of the first electrical part indicates that the first electrical part is functional, and finishing the chip. Also, the method may include the step of rejecting the first electrical part if the test result of the first electrical part indicates that the first electrical part is defective.
    • 7. 发明授权
    • Flash memory card expander
    • 闪存卡扩展器
    • US08282012B2
    • 2012-10-09
    • US12945722
    • 2010-11-12
    • Ben Wei ChenDavid SunGeorge Shiu
    • Ben Wei ChenDavid SunGeorge Shiu
    • G06K19/06
    • H05K5/0282H01R31/06
    • Method and system for expanding the memory capacity of devices that use flash memory cards. In one aspect, a memory card expander assembly includes an adaptor shaped to be connected to a memory card slot of a host device, and a receptacle assembly in communication with the adaptor and operative to be attached to the host device. The receptacle assembly includes an expanded memory card slot operative to connect to a memory card such that the host device can communicate with the connected memory card when the adaptor is connected to the memory card slot.
    • 扩展使用闪存卡的设备的内存容量的方法和系统。 在一个方面,一种存储卡扩展器组件包括被成形为连接到主机设备的存储卡插槽的适配器以及与适配器通信并且可操作地连接到主机设备的插座组件。 插座组件包括可操作地连接到存储卡的扩展的存储卡插槽,使得当适配器连接到存储卡插槽时,主机设备可与连接的存储卡通信。
    • 10. 发明授权
    • Leadframe semiconductor package stand and method for making the same
    • 引线框半导体封装架及其制造方法
    • US07781299B2
    • 2010-08-24
    • US11094557
    • 2005-03-31
    • Wei H. Koh
    • Wei H. Koh
    • H01L23/495H01L21/56H01L21/60
    • H01L23/49861H01L23/4951H01L23/49558H01L2924/0002Y10T29/4913Y10T29/49147H01L2924/00
    • A method is disclosed for making a leadframe package stand having application in semiconductor packaging and microelectronic assembly in which an IC device (e.g., a bare chip IC, a wafer level package, or a chipscale package) is received for electrical connection to a PWB or for vertical package over package stacking. Electrically conductive leadframe traces are arranged in an area array circuit pattern between outer leads at the periphery of the mold body of a leadframe for connection to the PWB to inner leads for connection to the IC device. The inner lead tips terminate at each side of the IC device in groups of parallel aligned rows and columns to facilitate connection to the IC device without using intermediate bonding wires. Prior to molding, the inner leads of the conductive traces are secured by sacrificial tie-bars or adhesive tape to prevent movement of the inner leads and possible short circuits during molding. A cavity is formed in the mold body during molding so as to lie above the inner leads. After molding, the sacrificial tie-bars are separated from the inner leads, and the IC device is located in the cavity to be assembled to the leadframe to complete a leadframe package.
    • 公开了一种用于制造半导体封装和微电子组件的引线框架封装架的方法,其中IC器件(例如,裸芯片IC,晶片级封装或芯片尺寸封装)被接收用于电连接到PWB或 用于垂直封装堆叠堆叠。 导电引线框架线路以引线框架的模体的周边的外引线之间的区域阵列电路图形布置,用于连接到PWB到用于连接到IC器件的内引线。 内部引线末端在IC器件的每一侧以平行排列的行和列组终止,以便于不使用中间接合线而连接到IC器件。 在模制之前,导电迹线的内部引线通过牺牲连接条或胶带固定,以防止内部引线的移动和模制期间可能的短路。 在模制过程中在模具体中形成空腔以便位于内部引线之上。 在模制之后,牺牲连接杆与内引线分离,并且IC器件位于腔中以组装到引线框架以完成引线框封装。