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1. 发明授权

US10990520B2 Method for gabage collecting for non-volatile memory 有权
公开(公告)号：US10990520B2
公开(公告)日：2021-04-27
申请号：US16214649
申请日：2018-12-10
申请人： Storart Technology Co., Ltd.
发明人： Bing-En Li , Hou-Yun Lee , Sei-Fer Wei
IPC分类号： G06F7/02 , G06F16/00 , G06F12/02 , G06F16/17
摘要： A method for garbage collecting for non-volatile memories are disclosed. The method includes steps: a) providing a SSD, connected to a host, containing a plurality of TLC blocks and SLC blocks; b) reading 3M TLC pages in a TLC block having data; c) moving valid data in the TLC blocks to at least one clean TLC block; d) sending a host program command of 1 page to the host; e) repeating step b) to step d) until valid data in 8 TLC blocks are moved; f) reading 1 SLC page in a SLC block having data; g) moving valid data in the SLC block to the at least one clean TLC block; h) sending a host program command of α page to the host; and i) repeating step f) to step h) until valid data in the SLC block having data are moved.

2. 发明授权

US09880831B2 Field firmware upgrading method and computer-readable medium 有权
公开(公告)号：US09880831B2
公开(公告)日：2018-01-30
申请号：US14934171
申请日：2015-11-06
申请人： STORART TECHNOLOGY CO. LTD.
发明人： Yi-Ming Wang , Wan-Chun Chang , Shih-Hung Fan
IPC分类号： G06F9/44 , G06F9/445
CPC分类号： G06F8/656 , G06F8/654 , G06F9/4406
摘要： A field firmware upgrading method is adapted in a field firmware upgrading system having a computing device and a storage device. First, the computing device is boot up to a real-time operating system (RTOS), wherein the RTOS and a firmware of the storage device are communicated with each other via a driver. The RTOS sends reading commands to the firmware, such that the firmware performs a reading operation meeting a prefix proceeding, wherein the prefix proceeding defines an order which specific logic block addresses (LBAs) are read. After the firmware performs the reading operation meeting the prefix proceeding, the RTOS sends writing commands to the firmware, such that the firmware performs a writing operation meeting a specific writing proceeding to write an firmware image file into the storage device beginning at a target LBA defined by the specific writing proceeding.

3. 发明申请

US20170070243A1 EARLY TERMINATION METHOD WITH RE-ENCODING SCHEME FOR DECODING OF ERROR CORRECTION CODE 审中-公开
标题翻译：具有用于解码错误校正码的重新编码方案的早期终止方法
公开(公告)号：US20170070243A1
公开(公告)日：2017-03-09
申请号：US14847207
申请日：2015-09-08
申请人： Storart Technology Co.,Ltd.
发明人： Jui Hui HUNG
IPC分类号： H03M13/45 , H03M13/37
CPC分类号： H03M13/458 , H03M13/3738 , H03M13/3753 , H03M13/3776
摘要： An early termination method with a re-encoding scheme for decoding of error correction codes is disclosed. The method includes the steps of: A. receiving soft values; B. processing hard decision on the soft value to determine a codeword; C. separating the codeword into a data part and a first parity part; D. re-encoding the data part to get a second parity part; E. checking if the first parity part and the second parity part are equivalent; and F. if a result of step E is yes, stopping decoding the codeword; if the result of step E is no, processing a decoding algorithm on the codeword. By this method, the received codeword still can be correctly decoded if there are many errors in the parity region and its decoding performance can be improved.
摘要翻译：公开了一种具有用于解码纠错码的重新编码方案的早期终止方法。该方法包括以下步骤：A.接收软值; B.处理硬判决软值确定码字; C.将码字分离成数据部分和第一奇偶校验部分; D.重新编码数据部分以获得第二个奇偶校验部分; E.检查第一奇偶校验部分和第二奇偶校验部分是否相等; 如果步骤E的结果为是，则停止解码码字; 如果步骤E的结果为否，则对码字进行解码算法处理。通过该方法，如果奇偶校验区域中存在许多错误并且可以提高其解码性能，则仍可以正确解码接收到的码字。

4. 发明授权

US09577672B2 Low density parity-check code decoder and decoding method thereof 有权
标题翻译：低密度奇偶校验码解码器及其解码方法
公开(公告)号：US09577672B2
公开(公告)日：2017-02-21
申请号：US14335327
申请日：2014-07-18
申请人： STORART TECHNOLOGY CO. LTD.
发明人： Jui-Hui Hung , Chih-Nan Yen
IPC分类号： H03M13/00 , H03M13/11 , H03M13/25 , H04L1/00 , G11B20/18
CPC分类号： H03M13/11 , G11B20/1833 , H03M13/1137 , H03M13/116 , H03M13/255 , H03M13/6566 , H04L1/0026 , H04L1/0041 , H04L1/0057
摘要： The present disclosure illustrates a low density parity-check code decoder adapted for decoding coding data having bit nodes and check nodes. The decoder includes a calculation module and a memory. The calculation module includes k calculation units and n shift units, and the memory includes n memory units. The memory is coupled to the calculation module. Each shift unit is one-to-many coupled to the k calculation units. The n memory units are coupled to the n shift units. The calculation module operatively divides the coding data into n first-bit-strings. The ith calculation unit operatively generates a second-bit-string by calculating ith bits of the n first-bit-strings. The jth shift unit operatively generates a third-bit-string upon receiving jth bits of the k second-bit-strings, and shifts the third-bit-string. The memory units are configured for storing the n shifted third-bit-strings respectively.
摘要翻译：本公开示出了适用于对具有位节点和校验节点的编码数据进行解码的低密度奇偶校验码解码器。解码器包括计算模块和存储器。计算模块包括k个计算单元和n个移位单元，并且存储器包括n个存储器单元。存储器耦合到计算模块。每个移位单元与k个计算单元耦合一对多。 n个存储器单元耦合到n个移位单元。计算模块将编码数据可操作地划分为n个第一比特串。第i个计算单元通过计算n个第一比特串的第i个比特来可操作地生成第二比特串。第j个移位单元在接收到k个第二比特串的第j个比特时可操作地生成第三比特串，并移位第三比特串。存储器单元被配置为分别存储n个移位的第三位串。

5. 发明申请

US20150318869A1 ENCODING AND SYNDROME COMPUTING CO-DESIGN CIRCUIT FOR BCH CODE AND METHOD FOR DECIDING THE SAME 有权
标题翻译：用于BCH代码的编码和综合计算协同设计电路及其决定方法
公开(公告)号：US20150318869A1
公开(公告)日：2015-11-05
申请号：US14265929
申请日：2014-04-30
申请人： STORART TECHNOLOGY CO.,LTD.
发明人： Jui Hui HUNG , Chih Nan YEN
IPC分类号： H03M13/15
CPC分类号： H03M13/152 , H03M13/157 , H03M13/1595 , H03M13/616
摘要： An encoding and syndrome computing co-design circuit for BCH code and a method for deciding the circuit are disclosed. The method includes the steps of: building up matrices of XR, XG and XS according to p parallel computations and 2t syndromes; building up FP; building up F′; building up F″; building up matrix of [XSRG F″]; and designing a circuit which fulfills the operation of [XSRG F″].
摘要翻译：公开了用于BCH码的编码和综合计算协同设计电路以及用于确定电路的方法。该方法包括以下步骤：根据p并行计算和2t综合征建立XR，XG和XS的矩阵; 建立FP; 建立F' 建立F“; 建立[XSRG F“]矩阵; 并设计满足[XSRG F“]操作的电路。

6. 发明授权

US09146857B2 Method for mapping management 有权
标题翻译：映射管理方法
公开(公告)号：US09146857B2
公开(公告)日：2015-09-29
申请号：US13589119
申请日：2012-08-18
申请人： Yen Chih Nan
发明人： Yen Chih Nan
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7201
摘要： A method for mapping management is disclosed. The steps of the method comprises sending data from a host; programming a host data a non-volatile storage device; updating a mapping address to a Physical Entry to Logical (PE2L) mapping table stored in a SRAM; updating a Physical Entry (PE) status table; checking if the PE2L mapping table is full; if no, loop to the step of programming a non-violate storage device; if yes, remove invalid entries in the PE2L mapping table and update the PE status table, and then run next step; transferring part of the PE2L mapping table to a Logical to Physical (L2P) mapping table stored in the non-volatile storage device; and programming the L2P mapping table to the non-volatile storage device and looping to the step of removing invalid entries in the PE2L mapping table and updating the PE status table.
摘要翻译：公开了一种映射管理方法。该方法的步骤包括从主机发送数据; 将主机数据编程为非易失性存储设备; 将映射地址更新为存储在SRAM中的物理入口到逻辑（PE2L）映射表; 更新物理条目（PE）状态表; 检查PE2L映射表是否已满; 如果没有，循环到编程非违规存储设备的步骤; 如果是，删除PE2L映射表中的无效条目，更新PE状态表，然后运行下一步; 将部分PE2L映射表传输到存储在非易失性存储设备中的逻辑到物理（L2P）映射表; 并将L2P映射表编程到非易失性存储设备，并循环到删除PE2L映射表中的无效条目并更新PE状态表。

7. 发明申请

US20150199282A1 SCRAMBLE RANDOM SEED PREDICTION METHOD WITH STORAGE DEVICE BUILT-IN DATA COPY BACK PROCEDURE 审中-公开
标题翻译：具有存储设备的可拉式随机种子预测方法内置数据复制过程
公开(公告)号：US20150199282A1
公开(公告)日：2015-07-16
申请号：US14157487
申请日：2014-01-16
申请人： Storart Technology Co., Ltd.
发明人： CHIH-NAN YEN , CHIEN-CHENG LIN , SZU-I YEH
IPC分类号： G06F12/14 , G06F21/60
CPC分类号： G06F12/1408 , G06F12/0246 , G06F2212/7202
摘要： A scramble random seed prediction method with the storage device built-in data copy back procedure is disclosed. The method may predict a scramble random seed before first time programming. The data may be programmed with the scramble random seed based on the pager number of the block B, not block A, before programming data to block A. After data is moved from block A to block B with the storage device built-in data copy back procedure, the data in block B may be have the best scramble random seed. Therefore, compared to the conventional method of scrambling data or data movement, the moved data of this invention may be much more stable with the storage device data copy back procedure.
摘要翻译：公开了具有存储装置内置数据复制程序的加扰随机种子预测方法。该方法可以在第一次编程之前预测加扰随机种子。在将数据编程到块A之前，可以使用基于块B的寻呼机号码而不是块A的加扰随机种子对数据进行编程。在数据从块A移动到块B之后，存储设备内置数据副本返回程序，块B中的数据可能具有最佳的加扰随机种子。因此，与传统的数据或数据移动的方法相比，本发明的移动数据可以通过存储设备数据复制过程更加稳定。

8. 发明授权

US08661301B1 Method for dodging bad page and bad block caused by suddenly power off 有权
标题翻译：避免突然断电引起的坏页和坏块的方法
公开(公告)号：US08661301B1
公开(公告)日：2014-02-25
申请号：US13607646
申请日：2012-09-07
申请人： Chi Nan Yen
发明人： Chi Nan Yen
IPC分类号： G11C29/00 , G06F13/00 , G06F9/34 , G06F1/00
CPC分类号： G11C16/22 , G11C29/52 , G11C29/82
摘要： A method for dodging bad page and bad block caused by suddenly power off is disclosed. This method is to avoid a new data from host program to potential hurt block or page caused by power off during NAND flash erasing or programming.
摘要翻译：公开了一种避免由于突然断电引起的坏页和坏块的方法。该方法是在NAND闪存擦除或编程期间避免主机程序中的新数据到电源关闭引起的潜在的受阻块或页面。

9. 发明授权

US09973212B2 Decoding algorithm with enhanced parity check matrix and re-encoding scheme for LDPC code 有权
公开(公告)号：US09973212B2
公开(公告)日：2018-05-15
申请号：US14847214
申请日：2015-09-08
申请人： Storart Technology Co., Ltd.
发明人： Jui Hui Hung
IPC分类号： H03M13/00 , H03M13/11 , H03M13/37
CPC分类号： H03M13/1108 , H03M13/116 , H03M13/1185 , H03M13/3776 , H03M13/6502 , H03M13/6544
摘要： A decoding algorithm with an enhanced parity check matrix and a re-encoding scheme for LDPC codes is disclosed. The decoding algorithm includes the steps of: providing the enhanced parity check matrix; receiving a message part of an original codeword encoded by a generator matrix from the enhanced parity check matrix; setting a LLR for each bit node of the enhanced parity check matrix; processing hard decision on the message part of the original codeword; encoding the message part of the original codeword by the generator matrix to generate a new codeword having a generated parity part; comparing the original parity part with the generated parity part to find out bits of difference; voting candidate error bits to choose the most probably erratic bits; modifying LLR of the chosen bits to have a modified codeword; and processing a conventional iterative decoding procedure on the modified codeword to have a processed codeword.

10. 发明申请

US20170371555A1 METHOD FOR REDUCING USE OF DRAM IN SSD AND THE SSD USING THE SAME 审中-公开
公开(公告)号：US20170371555A1
公开(公告)日：2017-12-28
申请号：US15189025
申请日：2016-06-22
申请人： Storart Technology Co.,Ltd.
发明人： Hou Yun LEE
IPC分类号： G06F3/06 , G11C7/10
CPC分类号： G06F3/0608 , G06F3/0638 , G06F3/065 , G06F3/068 , G06F3/0688 , G11C7/1072
摘要： A SSD and a method for reducing use of DRAM in the SSD are disclosed. The method includes the steps of: A. providing a referring table in a DRAM module of a SSD; B. providing a logical-to-physical address table in the DRAM module; C. receiving a command for accessing a target data in a target logical address of the SSD; D. checking if one physical address is stored in the logical-to-physical address table; E. executing the command by using the mapping data in the subgroup or copying a corresponding subgroup including one mapping data for the target logical address from the mapping table to the DRAM module via the referring table; and; and F. adding a target physical address of the DRAM module where the mapping data for the target logical address is stored to the logical-to-physical address table so that the target logical address is able to correspond thereto.

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