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1. 发明申请

US20190190543A1 LOW-DENSITY PARITY CHECK (LDPC) INCREMENTAL PARITY-CHECK MATRIX ROTATION 审中-公开
公开(公告)号：US20190190543A1
公开(公告)日：2019-06-20
申请号：US15849590
申请日：2017-12-20
申请人： QUALCOMM Incorporated
发明人： Chi-Yuen Young , Jaeyoung Kwak
IPC分类号： H03M13/00 , H03M13/11
CPC分类号： H03M13/616 , H03M13/1105 , H03M13/1137 , H03M13/116 , H03M13/118 , H03M13/1185 , H03M13/1188 , H03M13/6502 , H03M13/6516 , H03M13/6561 , H04L1/0041 , H04L1/0045
摘要： Aspects of the present disclosure relate to parity-check matrix (P-matrix) rotation in low-density parity check (LDPC) coding. The P-matrix rotation may be performed by a plurality of shift registers, where each shift register is configured to receive a respective set of bits corresponding to a respective column in the P-matrix. Each cycle, the shift registers may then incrementally rotate their respective sets of bits to achieve a respective shift amount up to a maximum shift amount per cycle. During a cycle, if the shift amount produced by a shift register results in a degree of rotation corresponding to an element within the respective column of the P-matrix, the shift register may output the rotated set of bits for further processing.

2. 发明申请

US20180337693A1 DATA PROCESSING DEVICE AND DATA PROCESSING METHOD 审中-公开
公开(公告)号：US20180337693A1
公开(公告)日：2018-11-22
申请号：US15980374
申请日：2018-05-15
申请人： Saturn Licensing LLC
发明人： Ryoji Ikegaya , Makiko Yamamoto , Yuji Shinohara
IPC分类号： H03M13/25 , H03M13/00 , H03M13/35 , H03M13/29 , H03M13/03 , H03M13/27 , H03M13/11 , H03M13/15
CPC分类号： H03M13/255 , H03M13/036 , H03M13/1137 , H03M13/1165 , H03M13/152 , H03M13/271 , H03M13/2906 , H03M13/356 , H03M13/618
摘要： The present technology relates to a data processing device and a data processing method capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code having a code length N of 64800 bits and a coding rate r of 9/15, 11/15, or 13/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of LDPC codes after the group-wise interleave is returned to an original sequence. The present technology, for example, can be applied to a case where data transmission using an LDPC code or the like is performed.

3. 发明申请

US20180287638A1 DATA PROCESSING DEVICE AND DATA PROCESSING METHOD 审中-公开
公开(公告)号：US20180287638A1
公开(公告)日：2018-10-04
申请号：US15935439
申请日：2018-03-26
申请人： SONY CORPORATION
发明人： Ryoji IKEGAYA , Makiko YAMAMOTO , Yuji SHINOHARA
IPC分类号： H03M13/11 , H04L1/00 , G06F11/10 , H03M13/00 , H03M13/35 , H03M13/29 , H03M13/27 , H03M13/25 , H03M13/03 , H03M13/15
CPC分类号： H03M13/1148 , G06F11/10 , H03M13/036 , H03M13/1137 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/271 , H03M13/2757 , H03M13/2778 , H03M13/2792 , H03M13/2906 , H03M13/356 , H03M13/616 , H04L1/00 , H04L1/0041 , H04L1/0057 , H04L1/0058 , H04L1/0071
摘要： The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 6/15, 8/15, or 10/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.

4. 发明授权

US09859922B2 Data processing device and data processing method 有权
公开(公告)号：US09859922B2
公开(公告)日：2018-01-02
申请号：US14784185
申请日：2014-04-21
申请人： SONY CORPORATION
发明人： Yuji Shinohara , Nabil Sven Loghin Muhammad , Lachlan Michael , Yuichi Hirayama , Makiko Yamamoto
IPC分类号： H03M13/11 , H03M13/00 , H03M13/27 , H04L1/00 , H03M13/25 , H03M13/35 , H03M13/15 , H03M13/29
CPC分类号： H03M13/1177 , H03M13/1137 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/271 , H03M13/2906 , H03M13/356 , H03M13/616 , H04L1/0041 , H04L1/0057
摘要： A code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15 is interchanged with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK. In the interchanging, when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a (#i +1)-th bit from a most significant bit of the 3 bits of code bits is set to a bit b#i, a (#i +1)-th bit from a most significant bit of 3 bits of symbol bits of the one symbol is set to a bit y#i, and a bit b0, a bit b1, and a bit b2 are interchanged with a bit y1, a bit y0, and a bit y2.

5. 发明授权

US09806742B2 Data processing device and data processing method 有权
公开(公告)号：US09806742B2
公开(公告)日：2017-10-31
申请号：US14782542
申请日：2014-04-21
申请人： Sony Corporation
发明人： Yuji Shinohara , Nabil Sven Loghin Muhammad , Lachlan Michael , Yuichi Hirayama , Makiko Yamamoto
IPC分类号： H03M13/11 , H03M13/00 , H03M13/25 , H03M13/27 , H03M13/29 , H03M13/35 , H04L1/00 , H03M13/09
CPC分类号： H03M13/1108 , H03M13/09 , H03M13/1137 , H03M13/1165 , H03M13/255 , H03M13/2707 , H03M13/271 , H03M13/2906 , H03M13/356 , H03M13/616 , H03M13/6552 , H03M13/6555 , H04L1/0057 , H04L1/0065 , H04L1/007 , H04L1/0071
摘要： In a transmitting device, in interchanging to interchange a code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 7/15 with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK, when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a bit b0, a bit b1, and a bit b2 are interchanged with a bit y1, a bit y0, and a bit y2, respectively. A position of the interchanged code bit obtained from data transmitted from the transmitting device is returned to an original position. The present technology is applicable to a case of transmitting data using an LDPC code, for example.

6. 发明申请

US20170141798A1 PUNCTURING FOR STRUCTURED LOW DENSITY PARITY CHECK (LDPC) CODES 审中-公开
公开(公告)号：US20170141798A1
公开(公告)日：2017-05-18
申请号：US15202207
申请日：2016-07-05
申请人： QUALCOMM Incorporated
发明人： Shrinivas KUDEKAR , Se Yong PARK , Alexandros MANOLAKOS , Krishna Kiran MUKKAVILLI , Vincent LONCKE , Joseph Binamira SORIAGA , Jing JIANG , Thomas Joseph RICHARDSON
IPC分类号： H03M13/25 , H03M13/00
CPC分类号： H03M13/6527 , H03M13/03 , H03M13/036 , H03M13/1102 , H03M13/1137 , H03M13/116 , H03M13/6362 , H04L1/0041 , H04L1/0045 , H04L1/0057 , H04L1/0069 , H04L1/1819
摘要： Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low density parity check (LDPC) codes. A method for wireless communications by wireless node is provided. The method generally includes encoding a set of information bits based on a LDPC code to produce a code word, the LDPC code defined by a matrix having a first number of variable nodes and a second number of check nodes, puncturing the code word to produce a punctured code word, wherein the puncturing is performed according to a first puncturing pattern designed to puncture bits corresponding to one or more of the variable nodes having a certain degree of connectivity to the check nodes, and transmitting the punctured code word

7. 发明申请

US20170063395A1 DESIGN OF DVB-S2 LDPC DECODER USING OVERLAPPED DECODING SCHEME 有权
标题翻译：使用重叠解码方案的DVB-S2 LDPC解码器的设计
公开(公告)号：US20170063395A1
公开(公告)日：2017-03-02
申请号：US15132585
申请日：2016-04-19
申请人： KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
发明人： Jun-Young WI , Jun Heo , Sung Won Kim
IPC分类号： H03M13/11 , H03M13/00
CPC分类号： H03M13/112 , H03M13/1137 , H03M13/1165
摘要： Provided is a low density parity check decoder, which includes a bit node calculating unit configured to calculate a bit node, a check node calculating unit configured to calculate a check node, a control unit configured to control calculation of the bit node and the check node, and a storage unit configured to store calculation values of the bit node or the check node, wherein the control unit calculates the bit node or the check node so that the node calculations are overlapped, by using an address offset value of the storage unit, thereby reducing a decoding time.
摘要翻译：提供了一种低密度奇偶校验解码器，其包括：被配置为计算比特节点的比特节点计算单元，被配置为计算校验节点的校验节点计算单元，被配置为控制比特节点和校验节点的计算的控制单元以及存储单元，其被配置为存储所述比特节点或所述校验节点的计算值，其中，所述控制单元通过使用所述存储单元的地址偏移值来计算所述比特节点或所述校验节点，使得所述节点计算重叠，从而减少了解码时间。

8. 发明授权

US09548759B1 Systems and methods for processing LDPC codes with different circulant sizes 有权
标题翻译：用于处理不同循环尺寸的LDPC码的系统和方法
公开(公告)号：US09548759B1
公开(公告)日：2017-01-17
申请号：US14554845
申请日：2014-11-26
申请人： Marvell International Ltd.
发明人： Farshid Rafiee Rad
IPC分类号： H03M13/11 , H03M13/37
CPC分类号： H03M13/116 , H03M13/1137 , H03M13/114 , H03M13/6516
摘要： Systems and methods are provided for decoding low density parity check (LDPC) codes with different circulant sizes using common decoding circuitry. The systems and methods include receiving a plurality of codewords corresponding to an LDPC code and determining a circulant size associated with the plurality of received codewords. In response to determining the circulant size associated with the plurality of received codewords, the systems and methods partition processing resources of the common decoding circuitry into a plurality of cells based on the determined circulant size and processing the plurality of received codewords simultaneously using the plurality of cells.
摘要翻译：提供了用于使用公共解码电路解码具有不同循环尺寸的低密度奇偶校验（LDPC）码的系统和方法。系统和方法包括接收对应于LDPC码的多个码字，并确定与多个接收码字相关联的循环大小。响应于确定与多个接收码字相关联的循环大小，系统和方法基于确定的循环大小将公共解码电路的处理资源划分为多个小区，并且使用多个接收码字同时处理多个接收码字细胞。

9. 发明授权

US09459956B2 Data decoder with trapping set flip bit mapper 有权
标题翻译：数据解码器与陷阱设置翻转位映射器
公开(公告)号：US09459956B2
公开(公告)日：2016-10-04
申请号：US13958162
申请日：2013-08-02
申请人： SEAGATE TECHNOLOGY LLC
发明人： Alexander Hubris , Zhengang Chen , AbdelHakim S. Alhussien , YingQuan Wu
IPC分类号： G06F11/10 , H03M13/00 , H03M13/11
CPC分类号： G06F11/1048 , G06F11/10 , H03M13/1102 , H03M13/1105 , H03M13/1137 , H03M13/114 , H03M13/1142 , H03M13/116 , H03M13/1171 , H03M13/6561 , H03M13/658
摘要： A low density parity check decoder includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages, a check node processor operable to generate the check node to variable node message vectors and to calculate checksums based on the variable node to check node messages, and a convergence detector and bit map generator operable to convergence of the perceived values and to generate at least one bit map that identifies variable nodes that are connected to check nodes with unsatisfied parity checks.
摘要翻译：低密度奇偶校验解码器包括可变节点处理器，其可操作以生成可变节点以校验节点消息，并且基于对可变节点消息的校验节点来计算感知值;校验节点处理器，可操作以将校验节点生成到可变节点消息向量;以及基于变量节点来计算校验和以检查节点消息;以及收敛检测器和位图生成器，其可操作用于感知值的收敛并生成至少一个位图，其识别连接到具有不满足奇偶校验检查的节点的变量节点。

10. 发明申请

US20160204802A1 Low-Power Low Density Parity Check Decoding 有权
标题翻译：低功耗低密度奇偶校验解码
公开(公告)号：US20160204802A1
公开(公告)日：2016-07-14
申请号：US15075255
申请日：2016-03-21
申请人： Maxlinear, Inc.
发明人： Mingrui Zhu , Curtis Ling , Timothy Gallagher
IPC分类号： H03M13/11
CPC分类号： H03M13/1114 , H03M13/1111 , H03M13/1125 , H03M13/1128 , H03M13/1131 , H03M13/1137 , H03M13/114 , H03M13/1165 , H03M13/616 , H03M13/6505 , H04L1/0045
摘要： In an example implementation of this disclosure, a message passing low density parity check (LDPC) decoder may, during decoding of a first group of bits, lock a first variable node upon a bit-value probability of the first variable node reaching a determined threshold, and lock a first check node upon all variable nodes connected to the first check node being locked. The LDPC decoder may cease decoding the first group of bits upon all variable nodes of the LDPC decoder being locked, all check nodes of the LDPC decoder being locked, reaching a maximum number of iterations, or reaching a timeout. During a particular iteration of the decoding of the first group of bits in which the first variable node is locked, the LDPC decoder may refrain from generating a bit-value probability for the locked first variable node.
摘要翻译：在本公开的示例实现中，在低位奇偶校验（LDPC）解码器的消息传送期间，在第一比特组解码期间，可以在第一可变节点达到确定阈值的比特值概率时锁定第一可变节点并且在连接到第一校验节点被锁定的所有变量节点上锁定第一校验节点。所述LDPC解码器可以在所述LDPC解码器的所有可变节点被锁定，所述LDPC解码器的所有校验节点被锁定，达到最大迭代次数或达到超时之后，停止解码所述第一组位。在第一可变节点被锁定的第一组比特的解码的特定迭代期间，LDPC解码器可以避免为锁定的第一可变节点生成比特值概率。

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