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1. 发明授权

US11342336B1 Integrated circuitry, memory circuitry, method used in forming integrated circuitry, and method used in forming memory circuitry 有权
公开(公告)号：US11342336B1
公开(公告)日：2022-05-24
申请号：US17166342
申请日：2021-02-03
申请人： Micron Technology, Inc.
发明人： Russell A. Benson
IPC分类号： H01L27/108
摘要： A method used in forming integrated circuitry comprises forming horizontally-spaced conductive vias above a substrate. Conducting material is formed directly above and directly against the conductive vias. The conducting material is patterned to form individual conductive lines that are individually directly above a plurality of the conductive vias that are spaced longitudinally-along the respective individual conductive line. The patterning forms the individual conductive lines to have longitudinally-alternating wider and narrower regions. The wider regions are directly above and directly against a top surface of individual of the conductive vias and are wider in a horizontal cross-section that is at the top surface than are the narrower regions in the horizontal cross-section. The narrower regions are longitudinally-between the wider regions. Other embodiments, including structure independent of method, are disclosed.

2. 发明授权

US10192873B2 Memory cell, an array of memory cells individually comprising a capacitor and a transistor with the array comprising rows of access lines and columns of digit lines, a 2T-1C memory cell, and methods of forming an array of capacitors and access transistors there-above 有权
公开(公告)号：US10192873B2
公开(公告)日：2019-01-29
申请号：US15818571
申请日：2017-11-20
申请人： Micron Technology, Inc.
发明人： Scott E. Sills , Durai Vishak Nirmal Ramaswamy
IPC分类号： H01L21/00 , H01L27/108 , H01L21/311 , H01L29/66 , H01L29/78 , H01L49/02 , H01L27/11507 , H01L27/11514 , H01L29/08 , H01L29/10
摘要： A method of forming an array of capacitors and access transistors there-above comprises forming access transistor trenches partially into insulative material. The trenches individually comprise longitudinally-spaced masked portions and longitudinally-spaced openings in the trenches longitudinally between the masked portions. The trench openings have walls therein extending longitudinally in and along the individual trench openings against laterally-opposing sides of the trenches. At least some of the insulative material that is under the trench openings is removed through bases of the trench openings between the walls and the masked portions to form individual capacitor openings in the insulative material that is lower than the walls. Individual capacitors are formed in the individual capacitor openings. A line of access transistors is formed in the individual trenches. The line of access transistors electrically couples to the individual capacitors that are along that line. Other aspects, including structure independent of method, are disclosed.

3. 发明授权

US09303914B2 Low vibration cryocooled system for low temperature microscopy and spectroscopy applications 有权
标题翻译：低振动低温冷却系统用于低温显微镜和光谱应用
公开(公告)号：US09303914B2
公开(公告)日：2016-04-05
申请号：US14297561
申请日：2014-06-05
申请人： Montana Instruments Corporation
发明人： Luke R. Mauritsen , Michael B. Simmonds , Dan Griffing
IPC分类号： F25B9/00 , F25B9/10 , F25B9/12 , F25B9/14 , F25D23/00 , F25B1/10 , F25B19/00 , G01C1/10 , F28F21/08 , G02B21/28
CPC分类号： B23P15/26 , B23K9/16 , C22F1/08 , F25B1/10 , F25B9/00 , F25B9/002 , F25B19/00 , F25D23/00 , F28F21/085 , G01C1/10 , G02B21/28 , Y10T29/49826
摘要： A vertical support rigidly mounted to a planar base positions and supports a cryocooler expander unit off axis and away from a sample to be examined. The sample support is likewise rigidly mounted to the planar base with a rigidly mounted sample housing therein. The cryocooler expander unit is suspended in the vertical support by spring dampening bearings. A pair of opposing flexible vacuum bellows connects the cryocooler expander unit to the sample housing and vertical support. This configuration isolates the sample from vibration. Flexible thermal links associated with a predictive electronic closed loop control sequence maintains sample temperature.
摘要翻译：刚性地安装到平面基座的垂直支撑件位置并且将低温冷却器膨胀器单元离轴并且远离被检查样品支撑。样品支撑件同样刚性地安装到平面底座上，其中刚性安装的样品壳体。低温冷却器膨胀机通过弹簧减振轴承悬挂在垂直支承中。一对相对的柔性真空波纹管将低温冷却器扩展器单元连接到样品壳体和垂直支撑。该配置将样品与振动隔离。与预测电子闭环控制序列相关联的柔性热链路保持样品温度。

4. 发明授权

US06844243B1 Methods of forming semiconductor constructions 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US06844243B1
公开(公告)日：2005-01-18
申请号：US10644560
申请日：2003-08-19
申请人： Fernando Gonzalez
发明人： Fernando Gonzalez
IPC分类号： H01L21/30 , H01L21/46 , H01L21/762 , H01L21/822 , H01L21/8238 , H01L27/06 , H01L27/108 , H01L31/00
CPC分类号： H01L21/8221 , H01L21/76254 , H01L27/0688
摘要： The invention includes a method of forming a semiconductor construction. A first substrate is provided which comprises silicon-containing structures separated from one another by an insulative material. The silicon-containing structures define an upper surface. A second semiconductor substrate is provided which comprises a monocrystalline material having a damage region therein. The second semiconductor substrate is bonded to the silicon-containing structures of the first substrate at the upper surface. The monocrystalline material is then cleaved along the damage region. The invention also encompasses a semiconductor construction comprising a first substrate having silicon-containing structures separated from one another by an insulative material, and a second substrate comprising a monocrystalline material. The silicon-containing structures of the first substrate define an upper surface, and the monocrystalline material of the second substrate is bonded over the silicon-containing structures at the upper surface.
摘要翻译：本发明包括形成半导体结构的方法。提供了第一衬底，其包括通过绝缘材料彼此分离的含硅结构。含硅结构限定了上表面。提供了第二半导体衬底，其包括其中具有损伤区域的单晶材料。第二半导体衬底在上表面与第一衬底的含硅结构结合。然后将单晶材料沿损伤区域切割。本发明还包括半导体结构，其包括具有通过绝缘材料彼此分离的含硅结构的第一衬底和包含单晶材料的第二衬底。第一衬底的含硅结构限定上表面，并且第二衬底的单晶材料在上表面上结合在含硅结构上。

5. 发明授权

US10283520B2 Elevationally-extending string of memory cells individually comprising a programmable charge storage transistor and method of forming an elevationally-extending string of memory cells individually comprising a programmable charge storage transistor 有权
公开(公告)号：US10283520B2
公开(公告)日：2019-05-07
申请号：US15208206
申请日：2016-07-12
申请人： Micron Technology, Inc.
发明人： John D. Hopkins , David Daycock , Yushi Hu , Christopher Larsen , Dimitrios Pavlopoulos
IPC分类号： H01L29/788 , H01L21/225 , H01L23/532 , H01L23/528 , H01L27/11582 , H01L27/11556 , H01L27/11519 , H01L27/11565 , H01L27/11568 , H01L27/11524
摘要： An elevationally-extending string of memory cells comprises an upper stack elevationally over a lower stack. The upper and lower stacks individually comprise vertically-alternating tiers comprising control gate material of individual charge storage field effect transistors vertically alternating with insulating material. An upper stack channel pillar extends through multiple of the vertically-alternating tiers in the upper stack and a lower stack channel pillar extends through multiple of the vertically-alternating tiers in the lower stack. Tunnel insulator, charge storage material, and control gate blocking insulator is laterally between the respective upper and lower stack channel pillars and the control gate material. A conductive interconnect comprising conductively-doped semiconductor material is elevationally between and electrically couples the upper and lower stack channel pillars together. The conductively-doped semiconductor material comprises a first conductivity-producing dopant. The conductive interconnect comprises a lower half thereof having a conductive region comprising at least one of (a) conductive material below the conductively-doped semiconductor material, or (b) a second non-p-type dopant within the conductively-doped semiconductor material that is different from the first dopant, the second dopant being present at an atomic concentration within the semiconductor material of at least 0.1%. Other embodiments, including method, are disclosed.

6. 发明授权

US10062426B2 Field effect transistor constructions with gate insulator having local regions radially there-through that have different capacitance at different circumferential locations relative to a channel core periphery 有权
公开(公告)号：US10062426B2
公开(公告)日：2018-08-28
申请号：US14260940
申请日：2014-04-24
申请人： Micron Technology, Inc.
发明人： Kamal M. Karda , Chandra Mouli , Durai Vishak Nirmal Ramaswamy , F. Daniel Gealy
IPC分类号： H01L29/423 , H01L29/78 , H01L29/788 , G11C11/22 , G11C16/04 , G11C16/10 , H01L27/11568 , H01L29/792 , H01L27/1159
CPC分类号： G11C11/223 , G11C11/2275 , G11C16/0466 , G11C16/10 , H01L27/11568 , H01L27/1159 , H01L29/42324 , H01L29/4234 , H01L29/42368 , H01L29/42376 , H01L29/42392 , H01L29/78391 , H01L29/788 , H01L29/7923
摘要： A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed.

7. 发明授权

US09121752B2 Acoustic measurement device 有权
标题翻译：声学测量装置
公开(公告)号：US09121752B2
公开(公告)日：2015-09-01
申请号：US12921389
申请日：2009-03-05
申请人： Toshiki Hanyu
发明人： Toshiki Hanyu
IPC分类号： H04R29/00 , G01H3/12 , H04R1/40
CPC分类号： G01H3/12 , H04R1/406
摘要： Provided is an acoustic measurement device capable of reducing the number of microphones while solving a problem of the dependency of interval between microphones on the frequency. The acoustic measurement device comprises a sound reception section (10) and a calculation section (20). The sound reception section includes a plurality of unidirectional microphones. The plurality of microphones of the sound reception section (10) are arranged such that the total sum of the unit vectors each facing the maximum sensitivity direction of the microphone is zero. The calculation section (20) calculates a particle velocity vector or acoustic intensity by multiplying respective unit vectors by measurement values of each of the plurality of microphones of the sound reception section and calculates acoustic information by vector-synthesizing the results.
摘要翻译：提供了一种能够减少麦克风数量同时解决麦克风之间的间隔对频率的依赖性的问题的声学测量装置。声学测量装置包括声音接收部分（10）和计算部分（20）。声音接收部分包括多个单向麦克风。声音接收部分（10）的多个麦克风被布置成使得每个面向麦克风的最大灵敏度方向的单位矢量的总和为零。计算部（20）通过将各单位向量乘以声音接收部的多个麦克风的测定值，计算出粒子速度矢量或声音强度，并通过对结果进行矢量合成来计算声学信息。

8. 发明授权

US07737559B2 Semiconductor constructions 有权
标题翻译：半导体结构
公开(公告)号：US07737559B2
公开(公告)日：2010-06-15
申请号：US11591017
申请日：2006-10-31
申请人： John Smythe
发明人： John Smythe
IPC分类号： H01L29/40 , H01L23/52 , H01L23/48
CPC分类号： H01L21/02126 , H01L21/02211 , H01L21/02222 , H01L21/288 , H01L21/316 , H01L21/32051 , H01L21/76831 , H01L21/76843 , H01L21/76877
摘要： The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to a material that forms a layer conformally along the treated surfaces. The material can, for example, comprise an aluminum-containing compound and one or both of silane and silazane. The invention also includes semiconductor constructions having conformal layers formed over liners containing one or more of titanium oxide, yttrium oxide, zirconium oxide and vanadium oxide.
摘要翻译：本发明包括在与半导体衬底相关联的波状表面形貌上保形地形成层的方法。起伏的表面形貌可以首先暴露于氧化钛，氧化钕，氧化钇，氧化锆和氧化钒中的一种或多种以处理表面，并且随后可以暴露于沿着被处理的表面共形形成层的材料。该材料可以例如包含含铝化合物和硅烷和硅氮烷中的一种或两种。本发明还包括在包含氧化钛，氧化钇，氧化锆和氧化钒中的一种或多种的衬垫上形成保形层的半导体结构。

9. 外观设计

USD557739S1 Book with cover flap 失效
公开(公告)号：USD557739S1
公开(公告)日：2007-12-18
申请号：US29214278
申请日：2004-10-01
申请人： Supriti Bharma
设计人： Supriti Bharma

10. 发明授权

US11963359B2 Integrated assemblies, and methods of forming integrated assemblies 有权
公开(公告)号：US11963359B2
公开(公告)日：2024-04-16
申请号：US18199630
申请日：2023-05-19
申请人： Micron Technology, Inc.
发明人： John D. Hopkins , Jordan D. Greenlee
IPC分类号： H10B43/27 , H10B41/27 , H10B41/41 , H10B41/50 , H10B43/40 , H10B43/50
CPC分类号： H10B43/27 , H10B41/27 , H10B41/41 , H10B41/50 , H10B43/40 , H10B43/50
摘要： Some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the first and second memory regions. The intermediate region has a first edge proximate the first memory region and has a second edge proximate the second memory region. Channel-material-pillars are arranged within the first and second memory regions. Conductive posts are arranged within the intermediate region. Doped-semiconductor-material is within the intermediate region and is configured as a substantially H-shaped structure having a first leg region along the first edge, a second leg region along the second edge, and a belt region adjacent the panel. Some embodiments include methods of forming integrated assemblies.

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