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1. 发明授权

US08874852B2 Data cache block deallocate requests in a multi-level cache hierarchy 有权
标题翻译：数据缓存块在多级缓存层次结构中释放请求
公开(公告)号：US08874852B2
公开(公告)日：2014-10-28
申请号：US13433048
申请日：2012-03-28
申请人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
发明人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/0804 , G06F12/121 , G06F12/122 , G06F12/126
摘要： In response to executing a deallocate instruction, a deallocation request specifying a target address of a target cache line is sent from a processor core to a lower level cache. In response, a determination is made if the target address hits in the lower level cache. If so, the target cache line is retained in a data array of the lower level cache, and a replacement order field of the lower level cache is updated such that the target cache line is more likely to be evicted in response to a subsequent cache miss in a congruence class including the target cache line. In response to the subsequent cache miss, the target cache line is cast out to the lower level cache with an indication that the target cache line was a target of a previous deallocation request of the processor core.
摘要翻译：响应于执行取消分配指令，将指定目标高速缓存行的目标地址的解除分配请求从处理器核发送到较低级高速缓存。作为响应，确定目标地址是否在较低级别高速缓存中。如果是这样，则目标高速缓存行被保留在较低级高速缓存的数据阵列中，并且更新较低级高速缓存的替换顺序字段，使得目标高速缓存行更可能响应于后续高速缓存未命中而被驱逐在包含目标缓存行的同余类中。响应于随后的高速缓存未命中，目标高速缓存行被推出到较低级缓存，指示目标高速缓存行是处理器核心的先前释放请求的目标。

2. 发明授权

US08850372B2 Method and system for performing invariant-guided abstraction of a logic design 有权
标题翻译：用于执行逻辑设计的不变引导抽象的方法和系统
公开(公告)号：US08850372B2
公开(公告)日：2014-09-30
申请号：US13656396
申请日：2012-10-19
申请人： International Business Machines Corporation
发明人： Jason Raymond Baumgartner , Alexander Ivrii , Arie Matsliah , Hari Mony
IPC分类号： G06F17/50 , G06F11/22 , G06F9/455
CPC分类号： G06F17/504
摘要： A computer-implemented method of invariant-guided abstraction includes a processor of a computing device generating one or more invariants corresponding to a design under verification by executing a proof algorithm with an input comprising at least a portion of the design and a specified resource limit. The method further includes deterministically assigning priority information to the one or more invariants generated and to components of the design referenced by said invariants. Finally, the method includes performing invariant-guided localization abstraction on the design model to generate an abstracted design model utilizing the assigned priority information as a localization hint that results in abstractions that are at least one of (a) smaller abstractions and (b) easier to verify abstractions.
摘要翻译：不变引导抽象的计算机实现的方法包括计算设备的处理器，其通过执行具有包括设计的至少一部分的输入和指定的资源限制的验证算法来生成对应于正在验证的设计的一个或多个不变量。该方法还包括确定性地将优先级信息分配给所生成的一个或多个不变量和由所述不变量引用的设计的组件。最后，该方法包括在设计模型上执行不变量引导定位抽象，以生成抽象设计模型，利用分配的优先级信息作为定位提示，导出抽象，其为（a）较小抽象中的至少一个，（b）更容易验证抽象。

3. 发明授权

US08849857B2 Techniques for performing data loss prevention 有权
标题翻译：防止数据丢失的技术
公开(公告)号：US08849857B2
公开(公告)日：2014-09-30
申请号：US12971082
申请日：2010-12-17
申请人： Gavin G. Bray , Lachlan A. Hillman
发明人： Gavin G. Bray , Lachlan A. Hillman
IPC分类号： G06F7/00 , G06F7/04 , G06Q10/10 , G06F21/60
CPC分类号： G06F21/604 , G06Q10/10
摘要： A technique for performing data loss prevention includes creating for a user, using a data processing system, respective permissive policies with a most permissive enforcement action for each content category of a resource. In this case, the content category includes at least two categories. The technique also includes forming, using the data processing system, a policy set based on the respective permissive policies. The technique further includes creating, using the data processing system, an effective policy from the policy set using a least permissive enforcement action. Finally, the technique includes applying, using the data processing system, the effective policy to determine whether a user action is permitted on the resource.
摘要翻译：用于执行数据丢失防止的技术包括为用户创建一个使用数据处理系统的各种允许的策略，对资源的每个内容类别具有最宽容的执行动作。在这种情况下，内容类别包括至少两个类别。该技术还包括使用数据处理系统形成基于各自的允许策略的策略集。该技术还包括使用数据处理系统，使用最不允许的执行动作从策略集中创建有效的策略。最后，该技术包括使用数据处理系统应用有效策略来确定资源上是否允许用户动作。

4. 发明授权

US08838901B2 Coordinated writeback of dirty cachelines 有权
标题翻译：脏缓存行的协调回写
公开(公告)号：US08838901B2
公开(公告)日：2014-09-16
申请号：US12775510
申请日：2010-05-07
申请人： David M. Daly , Benjiman L. Goodman , Hillery C. Hunter , William J. Starke , Jeffrey A. Stuecheli
发明人： David M. Daly , Benjiman L. Goodman , Hillery C. Hunter , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0804 , G06F12/0817 , G06F12/0897 , Y02D10/13
摘要： A data processing system includes a processor core and a cache memory hierarchy coupled to the processor core. The cache memory hierarchy includes at least one upper level cache and a lowest level cache. A memory controller is coupled to the lowest level cache and to a system memory and includes a physical write queue from which the memory controller writes data to the system memory. The memory controller initiates accesses to the lowest level cache to place into the physical write queue selected cachelines having spatial locality with data present in the physical write queue.
摘要翻译：数据处理系统包括处理器核心和耦合到处理器核心的高速缓存存储器层级。高速缓存存储器层级包括至少一个上级高速缓存和最低级高速缓存。存储器控制器耦合到最低级缓存和系统存储器，并且包括物理写队列，存储器控制器从该物理写队列将数据写入系统存储器。存储器控制器启动对最低级高速缓存的访问以放置到物理写入队列中，所选择的高速缓存线具有空间局部性，其中数据存在于物理写入队列中。

5. 发明授权

US08813216B2 Network security protection 有权
标题翻译：网络安全保护
公开(公告)号：US08813216B2
公开(公告)日：2014-08-19
申请号：US11014312
申请日：2004-12-16
申请人： William Joseph Bloemeke , Reid Anthony Cashion
发明人： William Joseph Bloemeke , Reid Anthony Cashion
IPC分类号： G06F9/00 , H04L29/06
CPC分类号： H04L63/0428 , H04L63/0209 , H04L63/0245 , H04L63/029 , H04L63/08 , H04L63/104 , H04L63/164 , H04L63/166
摘要： A method and system for providing security to a Network Job Entry (NJE) network. A first NJE node and a third NJE node are connected by a second NJE node. The second NJE node conducts a security check of NJE packets traveling between the first and third NJE nodes. The security check performed by the second NJE node includes checking the userid of the person or job that sent the NJE packet, as well as the NJE data type. The NJE data type may be classified by the type of operation being performed, such as a batch job, sysout, command, message, as well as what application is being used. In one preferred embodiment, the security check includes checking the security level of the source of the data being transferred, such as a sensitive application. The security check can be based on the size of the data packet, such that excessively large data packets from a particular user are not permitted to be transmitted outside a secure NJE network.
摘要翻译：一种用于向网络作业输入（NJE）网络提供安全性的方法和系统。第一NJE节点和第三NJE节点由第二NJE节点连接。第二个NJE节点对在第一和第三NJE节点之间行进的NJE分组进行安全检查。由第二NJE节点执行的安全检查包括检查发送NJE分组的人员或作业的用户ID以及NJE数据类型。 NJE数据类型可以根据正在执行的操作的类型进行分类，例如批处理作业，sysout，命令，消息以及正在使用的应用程序。在一个优选实施例中，安全检查包括检查正在传送的数据的源的安全级别，诸如敏感应用。安全检查可以基于数据分组的大小，使得来自特定用户的过大数据分组不被允许在安全的NJE网络之外传输。

6. 发明授权

US08806148B2 Forward progress mechanism for stores in the presence of load contention in a system favoring loads by state alteration 有权
标题翻译：在存在负载争用的情况下，通过状态改变有利于负载的系统中的商店的前进进展机制
公开(公告)号：US08806148B2
公开(公告)日：2014-08-12
申请号：US13679351
申请日：2012-11-16
申请人： International Business Machines Corporation
发明人： Guy L. Guthrie , Hien M. Le , Hugh Shen , Jeff A. Stuecheli , Derek E Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F2212/1008 , G06F2212/1016
摘要： A multiprocessor data processing system includes a plurality of cache memories including a cache memory. The cache memory issues a read-type operation for a target cache line. While waiting for receipt of the target cache line, the cache memory monitors to detect a competing store-type operation for the target cache line. In response to receiving the target cache line, the cache memory installs the target cache line in the cache memory, and sets a coherency state of the target cache line installed in the cache memory based on whether the competing store-type operation is detected.
摘要翻译：多处理器数据处理系统包括包括高速缓存存储器的多个高速缓存存储器。缓存存储器为目标高速缓存行发出读取类型操作。在等待接收目标高速缓存行的同时，高速缓冲存储器监视以检测目标高速缓存行的竞争存储类型操作。响应于接收到目标高速缓存行，高速缓存存储器将目标高速缓存行安装在高速缓冲存储器中，并且基于是否检测到竞争存储类型操作来设置安装在高速缓冲存储器中的目标高速缓存行的一致性状态。

7. 发明授权

US08799589B2 Forward progress mechanism for stores in the presence of load contention in a system favoring loads 有权
公开(公告)号：US08799589B2
公开(公告)日：2014-08-05
申请号：US13679247
申请日：2012-11-16
申请人： International Business Machines Corporation
发明人： Guy L. Guthrie , Hien M. Le , Jeff A. Stuecheli , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0811
摘要： A multiprocessor data processing system includes a plurality of cache memories including a cache memory. In response to the cache memory detecting a storage-modifying operation specifying a same target address as that of a first read-type operation being processed by the cache memory, the cache memory provides a retry response to the storage-modifying operation. In response to completion of the read-type operation, the cache memory enters a referee mode. While in the referee mode, the cache memory temporarily dynamically increases priority of any storage-modifying operation targeting the target address in relation to any second read-type operation targeting the target address.

8. 发明授权

US08793685B2 Techniques for operating virtual switches in a virtualized computing environment 有权
标题翻译：在虚拟化计算环境中操作虚拟交换机的技术
公开(公告)号：US08793685B2
公开(公告)日：2014-07-29
申请号：US13107433
申请日：2011-05-13
申请人： Jayakrishna Kidambi , Amitabha Biswas , John Buswell , Dorit Rond
发明人： Jayakrishna Kidambi , Amitabha Biswas , John Buswell , Dorit Rond
IPC分类号： G06F9/455
CPC分类号： H04L49/70 , H04L49/351 , H04L49/65
摘要： A technique for operating a virtual switch includes determining network connection requirements for virtual machines controlled by a virtual machine monitor. Resources available, for processing data traffic of the virtual machines, are also determined. Finally, based on the network connection requirements and the resources available, a port of a virtual switch is selected to operate as a virtual Ethernet bridge or a virtual Ethernet port aggregator.
摘要翻译：用于操作虚拟交换机的技术包括确定由虚拟机监视器控制的虚拟机的网络连接要求。还可以确定可用于处理虚拟机的数据流量的资源。最后，根据网络连接要求和可用资源，选择虚拟交换机的端口作为虚拟以太网桥或虚拟以太网端口聚合器。

9. 发明授权

US08793632B2 Techniques for electromigration stress determination in interconnects of an integrated circuit 有权
标题翻译：集成电路互连中电迁移应力测定技术
公开(公告)号：US08793632B2
公开(公告)日：2014-07-29
申请号：US13964344
申请日：2013-08-12
申请人： Freescale Semiconductor, Inc.
发明人： Ertugrul Demircan , Mehul D. Shroff
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , G06F2217/82
摘要： In one or more embodiments, one or more methods, processes, and/or systems described can determine stress failures in interconnect segments of integrated circuit designs and correct those failure via modifying the interconnect segments of the integrated circuit designs with one or more additions to the interconnect segments of the integrated circuit designs. Potentials can be received from a simulation, and one or more failures of an interconnect segment can be determined via the potentials from the simulation. For example, a failure can be determined via a comparison with a potential from the simulation and a critical potential. An interconnect segment can be modified with a stub such that a comparison with a potential from the simulation and a critical potential to provide a non-failing, modified interconnect segment.
摘要翻译：在一个或多个实施例中，所描述的一个或多个方法，过程和/或系统可以确定集成电路设计的互连部分中的应力故障，并通过修改集成电路设计的互连部分来校正那些故障，其中一个或多个添加到互连部分的集成电路设计。可以从仿真接收电位，并且可以通过仿真的电位来确定互连段的一个或多个故障。例如，可以通过与模拟的潜力和临界电位的比较来确定故障。可以使用存根修改互连段，以便与来自仿真的电位进行比较以及提供非故障修改的互连段的临界电位。

10. 发明授权

US08787561B2 Techniques for implementing adaptation control of an echo canceller to facilitate detection of in-band signals 有权
标题翻译：用于实现回波消除器的自适应控制以便于检测带内信号的技术
公开(公告)号：US08787561B2
公开(公告)日：2014-07-22
申请号：US12768366
申请日：2010-04-27
申请人： Roman A. Dyba , Wen Wu Su , Hongyang Deng
发明人： Roman A. Dyba , Wen Wu Su , Hongyang Deng
IPC分类号： H04M9/08
CPC分类号： H04B3/23
摘要： A technique for detecting in-band signaling tones in a communication system includes performing a first adaptation of an adaptive filter of an echo canceller in response to detection of a far-end harmonic signal. In this case, the adaptive filter provides an echo estimation signal. The technique also includes subtracting the echo estimation signal from a near-end signal that includes one or more in-band signaling tones to provide an error signal. The technique further includes detecting, using a tone detector, the one or more in-band signaling tones in the error signal.
摘要翻译：用于检测通信系统中的带内信令音的技术包括：响应于远端谐波信号的检测，执行回波消除器的自适应滤波器的第一自适应。在这种情况下，自适应滤波器提供回波估计信号。该技术还包括从包括一个或多个带内信令音调的近端信号中减去回波估计信号以提供误差信号。该技术还包括使用音调检测器检测误差信号中的一个或多个带内信令音调。

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