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1. 发明授权

US08930625B2 Weighted history allocation predictor algorithm in a hybrid cache 有权
标题翻译：混合高速缓存中加权历史分配预测算法
公开(公告)号：US08930625B2
公开(公告)日：2015-01-06
申请号：US13611614
申请日：2012-09-12
申请人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
发明人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/122 , G06F12/0897 , G06F12/121
摘要： A mechanism is provided for weighted history allocation prediction. For each member in a plurality of members in a lower level cache, an associated reference counter is initialized to an initial value based on an operation type that caused data to be allocated to a member location of the member. For each access to the member in the lower level cache, the associated reference counter is incremented. Responsive to a new allocation of data to the lower level cache and responsive to the new allocation of data requiring the victimization of another member in the lower level cache, a member of the lower level cache is identified that has a lowest reference count value in its associated reference counter. The member with the lowest reference count value in its associated reference counter is then evicted.
摘要翻译：提供了一种用于加权历史分配预测的机制。对于较低级缓存中的多个成员中的每个成员，相关联的引用计数器基于导致数据被分配给成员的成员位置的操作类型被初始化为初始值。对于对较低级缓存中的成员的每次访问，相关联的引用计数器递增。响应于对低级缓存的新数据分配并响应于需要在较低级别高速缓存中另一成员受害的数据的新分配，识别出在其级别缓存中具有最低参考计数值的成员相关参考计数器。然后将其相关参考计数器中具有最低参考计数值的成员逐出。

2. 发明授权

US08843707B2 Dynamic inclusive policy in a hybrid cache hierarchy using bandwidth 有权
标题翻译：使用带宽的混合缓存层次结构中的动态包容性策略
公开(公告)号：US08843707B2
公开(公告)日：2014-09-23
申请号：US13315395
申请日：2011-12-09
申请人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
发明人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
IPC分类号： G06F13/00
CPC分类号： G06F12/0897 , G06F2212/502
摘要： A mechanism is provided for dynamic cache allocation using bandwidth. A bandwidth between a higher level cache and a lower level cache is monitored. Responsive to bandwidth usage between the higher level cache and the lower level cache being below a predetermined low bandwidth threshold, the higher level cache and the lower level cache are set to operate in accordance with a first allocation policy. Responsive to bandwidth usage between the higher level cache and the lower level cache being above a predetermined high bandwidth threshold, the higher level cache and the lower level cache are set to operate in accordance with a second allocation policy.
摘要翻译：提供了一种使用带宽进行动态高速缓存分配的机制。监视高级缓存和较低级别缓存之间的带宽。响应于较高级别高速缓存和较低级别高速缓存之间的带宽使用低于预定低带宽阈值，高级缓存和下级高速缓存被设置为根据第一分配策略进行操作。响应于高级缓存和低级高速缓存之间的带宽使用高于预定高带宽阈值，高级缓存和下级高速缓存被设置为根据第二分配策略进行操作。

3. 发明申请

US20130151790A1 Efficient Storage of Meta-Bits Within a System Memory 失效
公开(公告)号：US20130151790A1
公开(公告)日：2013-06-13
申请号：US13611909
申请日：2012-09-12
申请人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
发明人： John S. Dodson , Benjiman L. Goodman , Steven J. Hnatko , Kenneth L. Wright
IPC分类号： G06F12/08
CPC分类号： G06F11/1076 , G06F11/1064 , G06F12/0815 , G06F12/0895 , G11C2029/0411
摘要： Mechanisms are provided for efficient storage of meta-bits within a system memory. The mechanisms combine an L/G bit and an SUE bit to form meta-bits. The mechanisms then determine the local/global state of a cache line on the first cycle of data. The mechanisms forward the data to the requesting cache, and the requesting cache may reissue the request globally based on the local/global state of the cache line. The mechanisms then determine the special uncorrectable error state of the cache line on the second or subsequent cycle of data. The mechanisms perform error processing regardless of whether the request was reissued globally.

4. 发明申请

US20120311248A1 CACHE LINE LOCK FOR PROVIDING DYNAMIC SPARING 审中-公开
标题翻译：缓存行锁提供动态空间
公开(公告)号：US20120311248A1
公开(公告)日：2012-12-06
申请号：US13152861
申请日：2011-06-03
申请人： Benjiman L. Goodman
发明人： Benjiman L. Goodman
IPC分类号： G06F12/08 , G06F12/02
CPC分类号： G06F12/126
摘要： A system that includes a memory, a cache, a purge mechanism, and a memory interface mechanism. The memory includes a failing memory element at a failing memory location. The cache is configured for storing corrected contents of the failing memory element in a locked state, with the corrected contents stored in a first cache line. The purge mechanism is configured for selecting and removing cache lines that are not in the locked state from the cache to make room for new cache allocations. The memory interface mechanism is configured for receiving a request to access the failing memory location, determining that corrected contents of the failing memory location are stored in first cache line in the cache, and accessing the first cache line in the cache.
摘要翻译：包括内存，缓存，清除机制和内存接口机制的系统。存储器包括在故障存储器位置处的故障存储器元件。高速缓存被配置为将失败的存储器元件的校正内容存储在锁定状态，其中校正的内容存储在第一高速缓存行中。清除机制被配置用于从高速缓存中选择和去除不处于锁定状态的高速缓存行，以便为新的高速缓存分配腾出空间。存储器接口机构被配置为用于接收访问故障存储器位置的请求，确定故障存储器位置的校正内容被存储在高速缓存中的第一高速缓存行中，以及访问高速缓存中的第一高速缓存行。

5. 发明授权

US08234612B2 Cone-aware spare cell placement using hypergraph connectivity analysis 有权
标题翻译：使用超图连接性分析的锥形识别备用单元布局
公开(公告)号：US08234612B2
公开(公告)日：2012-07-31
申请号：US12862949
申请日：2010-08-25
申请人： Benjiman L. Goodman , Nathaniel D. Hieter , Jeremy T. Hopkins , Samuel I. Ward
发明人： Benjiman L. Goodman , Nathaniel D. Hieter , Jeremy T. Hopkins , Samuel I. Ward
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/02 , G06F2217/72
摘要： Spare cells are placed in an IC design by assigning different spare utilization rates to logic cones, applying the rates to corresponding spare cell regions surrounding cells in the cones, identifying any overlap of regions from different logic cones, and inserting a spare cell at the overlapping region having the highest spare utilization rate. The best location for the spare cell is computed using a hypergraph wherein the cells are edges and the regions are nodes. Any node that is dominated by another node is removed and its edge is extended to the dominating node. The spare cell is inserted in the region having the most edges (the edges can be weighted). The process is repeated iteratively, updating the hypergraph by removing nodes connected to spare cell location, and inserting the next spare cell at a region corresponding to the node which then has the greatest number of connected edges.
摘要翻译：通过向逻辑锥分配不同的备用利用率来将备用单元放置在IC设计中，将速率应用于圆锥体中的小区周围的相应备用单元区域，识别来自不同逻辑锥的区域的任何重叠，以及在重叠处插入备用单元具有最高备用利用率的区域。使用超图来计算备用单元的最佳位置，其中单元是边缘，并且区域是节点。由另一个节点主导的任何节点被去除，其边缘被扩展到主导节点。备用单元插入具有最多边缘的区域（边缘可以加权）。该过程重复地重复，通过去除连接到备用单元位置的节点来更新超图，并且将下一个备用单元插入到与具有最大连接边数的节点相对应的区域。

6. 发明授权

US07925948B2 System and method for power reduction through power aware latch weighting 有权
标题翻译：通过功率感知锁存器加权降低功耗的系统和方法
公开(公告)号：US07925948B2
公开(公告)日：2011-04-12
申请号：US12206789
申请日：2008-09-09
申请人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, Jr.
发明人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, Jr.
IPC分类号： G01R31/28
CPC分类号： G06F11/263 , G01R31/3183
摘要： A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. A don't-care analysis module identifies absolute don't-care latches within the DUT, assigns a weighted value to the bit positions of identified don't-care latches, and identifies absolute don't-care bits within a general test pattern. The circuit analysis module replaces identified absolute don't-care bits in the general test pattern according to the weighted value of the associated bit position, generating a weighted test pattern. A test vector module generates a test vector based on the weighted test pattern and an input module applies the test vector to the DUT.
摘要翻译：一种系统包括被配置为分析待测器件（DUT）的电路分析模块，该DUT包括在扫描链中耦合在一起的多个锁存器。不需要的分析模块识别DUT内的绝对不需要的锁存器，为所识别的不可用锁存器的位置分配一个加权值，并在一般测试中识别绝对不需要的位模式。电路分析模块根据相关位位置的加权值替代通用测试模式中识别的绝对不关心位，生成加权测试模式。测试向量模块基于加权测试模式生成测试向量，并且输入模块将测试向量应用于DUT。

7. 发明申请

US20100268995A1 HARDWARE PROCESS TRACE FACILITY 有权
标题翻译：硬件工艺跟踪设备
公开(公告)号：US20100268995A1
公开(公告)日：2010-10-21
申请号：US12425075
申请日：2009-04-16
申请人： Benjiman L. Goodman , Sertac Cakici , Samuel I. Ward , Linton B. Ward, JR.
发明人： Benjiman L. Goodman , Sertac Cakici , Samuel I. Ward , Linton B. Ward, JR.
IPC分类号： G06F11/07
CPC分类号： G06F11/349 , G06F2201/87
摘要： A method for tracing thread bus transactions in a multiprocessor system comprises decoding, by a processor, a first thread instruction of a thread, the thread comprising an ordered series of thread instructions. In the event the first thread instruction is a set bus trace enable bit (BTEB) instruction, the processor sets a bus trace enable bit corresponding to the thread. In the event the BTEB is set, the processor determines whether the first thread instruction is a trace-eligible instruction and, in the event the first thread instruction is a trace-eligible instruction, and the BTEB is set, the processor sets a snoop tag trace enable bit (STTEB). A hardware trace monitor (HTM) monitors bus transactions, each bus transaction comprising a STTE. In the event a monitored bus transaction comprises a set STTEB, the HTM stores the bus transaction as trace data. In the event a monitored bus transaction comprises a reset STTEB, the HTM does not store the bus transaction as trace data.
摘要翻译：用于在多处理器系统中跟踪线程总线事务的方法包括由处理器解码线程的第一线程指令，所述线程包括有序序列的线程指令。在第一个线程指令是一个设置的总线跟踪使能位（BTEB）指令的情况下，处理器设置与线程相对应的总线跟踪使能位。在设置BTEB的情况下，处理器确定第一个线程指令是否是符合条件的指令，并且在第一个线程指令是符合跟踪条件的指令的情况下，并且BTEB被设置，处理器设置一个窥探标记跟踪使能位（STTEB）。硬件跟踪监视器（HTM）监视总线事务，每个总线事务包括STTE。在监控总线事务包括一组STTEB的情况下，HTM将总线事务存储为跟踪数据。在监控总线事务包括复位STTEB的情况下，HTM不将总线事务存储为跟踪数据。

8. 发明申请

US20100064190A1 System and Method for Power Reduction Through Power Aware Latch Weighting of Complex Sub-Circuits 有权
标题翻译：通过电力方面的功率降低系统和方法，复杂子电路的锁存加权
公开(公告)号：US20100064190A1
公开(公告)日：2010-03-11
申请号：US12206781
申请日：2008-09-09
申请人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, JR.
发明人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, JR.
IPC分类号： G01R31/3185 , G06F11/267
CPC分类号： G01R31/318536
摘要： A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. The circuit analysis module analyzes a DUT for sub-circuits within the DUT and identifies a logical description of identified sub-circuits. A don't-care analysis module couples to the circuit analysis module identifies absolute don't-care latches associated with the identified sub-circuits. A sub-circuit exception module couples to the circuit analysis module and selects weighted input values for an identified sub-circuit, based on the identified absolute don't-care latches and the logical description of the identified sub-circuit. The sub-circuit exception module stores the selected weighted input values for the sub-circuit and associates the selected weighted input values with the logical description.
摘要翻译：一种系统包括被配置为分析待测器件（DUT）的电路分析模块，该DUT包括在扫描链中耦合在一起的多个锁存器。电路分析模块分析DUT内的子电路的DUT，并识别所识别的子电路的逻辑描述。不需要的分析模块耦合到电路分析模块，识别与所识别的子电路相关的绝对不需要的锁存器。子电路异常模块耦合到电路分析模块，并且基于所识别的绝对不需要的锁存器和所识别的子电路的逻辑描述来选择所识别的子电路的加权输入值。子电路异常模块存储用于子电路的选择的加权输入值，并将所选择的加权输入值与逻辑描述相关联。

9. 发明申请

US20100064189A1 System and Method for Power Reduction Through Power Aware Latch Weighting 有权
标题翻译：通过电源意识锁定加权降低功耗的系统和方法
公开(公告)号：US20100064189A1
公开(公告)日：2010-03-11
申请号：US12206789
申请日：2008-09-09
申请人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, JR.
发明人： Samuel I. Ward , Benjiman L. Goodman , Joshua P. Hernandez , Linton B. Ward, JR.
IPC分类号： G06F11/00
CPC分类号： G06F11/263 , G01R31/3183
摘要： A system comprises a circuit analysis module configured to analyze a device under test (DUT), the DUT comprising a plurality of latches coupled together in a scan chain. A don't-care analysis module identifies absolute don't-care latches within the DUT, assigns a weighted value to the bit positions of identified don't-care latches, and identifies absolute don't-care bits within a general test pattern. The circuit analysis module replaces identified absolute don't-care bits in the general test pattern according to the weighted value of the associated bit position, generating a weighted test pattern. A test vector module generates a test vector based on the weighted test pattern and an input module applies the test vector to the DUT.
摘要翻译：一种系统包括被配置为分析待测器件（DUT）的电路分析模块，该DUT包括在扫描链中耦合在一起的多个锁存器。不需要的分析模块识别DUT内的绝对不需要的锁存器，为所识别的不可用锁存器的位置分配一个加权值，并在一般测试中识别绝对不需要的位模式。电路分析模块根据相关位位置的加权值替代通用测试模式中识别的绝对不关心位，生成加权测试模式。测试向量模块基于加权测试模式生成测试向量，并且输入模块将测试向量应用于DUT。

10. 发明授权

US07484042B2 Data processing system and method for predictively selecting a scope of a prefetch operation 失效
标题翻译：用于预测性地选择预取操作的范围的数据处理系统和方法
公开(公告)号：US07484042B2
公开(公告)日：2009-01-27
申请号：US11465587
申请日：2006-08-18
申请人： Benjiman L. Goodman , William J. Starke , Jeffrey A. Stuecheli
发明人： Benjiman L. Goodman , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F13/00
CPC分类号： G06F12/0862
摘要： A data processing system includes at least first and second coherency domains each containing at least one processing unit, an interconnect fabric coupling the first and second coherency domains, and a cache memory within the first coherency domain. The cache memory comprises a data array, a cache directory of contents of the data array, and a cache controller including a prefetch predictor. The prefetch predictor determines a predicted scope of broadcast on the interconnect fabric for a first prefetch operation having a first target address based upon a scope of a previous second prefetch operation having a different second target address. The cache controller issues the first prefetch operation on the interconnect fabric with the predicted scope.
摘要翻译：数据处理系统至少包括第一和第二相关域，每个域包含至少一个处理单元，耦合第一和第二相干域的互连结构以及第一相干域内的高速缓冲存储器。高速缓冲存储器包括数据阵列，数据阵列的内容的高速缓存目录以及包括预取预测器的高速缓存控制器。预取预测器基于具有不同的第二目标地址的先前的第二预取操作的范围来确定具有第一目标地址的第一预取操作的互连结构上的广播的预测范围。高速缓存控制器以预测的范围在互连结构上发出第一个预取操作。

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