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1. 发明申请

US20110267093A1 TESTABLE INTEGRATED CIRCUIT, SYSTEM IN PACKAGE AND TEST INSTRUCTION SET 有权
标题翻译：可测试的集成电路，封装和测试指令系统
公开(公告)号：US20110267093A1
公开(公告)日：2011-11-03
申请号：US13110408
申请日：2011-05-18
申请人： Fransciscus G. M., De Jong , Alexander Biewenga
发明人： Fransciscus G. M., De Jong , Alexander Biewenga
IPC分类号： G01R31/26
CPC分类号： G01R31/318555 , G01R31/318558
摘要： An integrated circuit die includes a plurality of interconnects including a first test data input, a second test data input and a test data output, and a test arrangement for testing the integrated circuit die. The test arrangement includes a further multiplexer coupled to the test data output, a multiplexer coupled to the first test data input and the second test data input, a plurality of shift registers including an instruction register, each of the shift registers being coupled between the multiplexer and the further multiplexer and a controller for controlling the multiplexer and the further multiplexer in response to the instruction register. Such a test arrangement facilitates JTAG compliant testing of a system in package by providing a direct connection between the SiP test data input pin and the second test data input of the IC die, and the SiP test data output pin and the test data output of the IC die, thus facilitating the bypassing of other test arrangements in the SiP.
摘要翻译：集成电路管芯包括包括第一测试数据输入，第二测试数据输入和测试数据输出的多个互连以及用于测试集成电路管芯的测试装置。测试装置包括耦合到测试数据输出的另一个多路复用器，耦合到第一测试数据输入和第二测试数据输入的多路复用器，包括指令寄存器的多个移位寄存器，每个移位寄存器耦合在多路复用器以及另外的多路复用器和用于响应于指令寄存器控制多路复用器和另外的多路复用器的控制器。这样的测试装置通过提供SiP测试数据输入引脚和IC芯片的第二测试数据输入之间的直接连接以及SiP测试数据输出引脚和测试数据输出的测试数据输出来促进封装中的系统的JTAG兼容性测试 IC芯片，从而有助于绕过SiP中的其他测试装置。

2. 发明授权

US07948243B2 Testable integrated circuit, system in package and test instruction set 有权
标题翻译：可测试集成电路，封装中的系统和测试指令集
公开(公告)号：US07948243B2
公开(公告)日：2011-05-24
申请号：US11996320
申请日：2006-07-20
申请人： Fransciscus G. M. De Jong , Alexander Biewenga
发明人： Fransciscus G. M. De Jong , Alexander Biewenga
IPC分类号： G01R31/02
CPC分类号： G01R31/318555 , G01R31/318558
摘要： An integrated circuit die includes first and second test data inputs, a test data output, and a test arrangement for testing the integrated circuit die. The test arrangement includes a multiplexer coupled to the first and second test data inputs, a further multiplexer coupled to the test data output, a plurality of shift registers including an instruction register, each of the shift registers being coupled between the multiplexer and the further multiplexer, and a controller for controlling the multiplexers in response to the instruction register. Such a test arrangement facilitates JTAG compliant testing of a system in package (SiP) by providing a direct connection between the SiP test data input pin and the second test data input of the IC die, and the SiP test data output pin and the test data output of the IC die, thus facilitating the bypassing of other test arrangements in the SiP.
摘要翻译：集成电路管芯包括第一和第二测试数据输入，测试数据输出以及用于测试集成电路管芯的测试装置。测试装置包括耦合到第一和第二测试数据输入的多路复用器，耦合到测试数据输出的另一多路复用器，包括指令寄存器的多个移位寄存器，每个移位寄存器耦合在多路复用器和另一多路复用器以及控制器，用于响应于指令寄存器来控制多路复用器。这种测试装置通过提供SiP测试数据输入引脚和IC芯片的第二测试数据输入之间的直接连接以及SiP测试数据输出引脚和测试数据来促进封装系统（SiP）中的JTAG兼容性测试 IC芯片的输出，从而有助于绕过SiP中的其他测试装置。

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