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1. 发明申请

US20110078381A1 Cache Operations and Policies For A Multi-Threaded Client 有权
标题翻译：多线程客户端的缓存操作和策略
公开(公告)号：US20110078381A1
公开(公告)日：2011-03-31
申请号：US12890476
申请日：2010-09-24
申请人： Steven James HEINRICH , Alexander L. Minkin , Brett W. Coon , Rajeshwaran Selvanesan , Robert Steven Glanville , Charles McCarver , Anjana Rajendran , Stewart Glenn Carlton , John R. Nickolls , Brian Fahs
发明人： Steven James HEINRICH , Alexander L. Minkin , Brett W. Coon , Rajeshwaran Selvanesan , Robert Steven Glanville , Charles McCarver , Anjana Rajendran , Stewart Glenn Carlton , John R. Nickolls , Brian Fahs
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0842 , G06F12/0897
摘要： A method for managing a parallel cache hierarchy in a processing unit. The method including receiving an instruction that includes a cache operations modifier that identifies a level of the parallel cache hierarchy in which to cache data associated with the instruction; and implementing a cache replacement policy based on the cache operations modifier.
摘要翻译：一种用于在处理单元中管理并行高速缓存层级的方法。该方法包括接收包括高速缓存操作修饰符的指令，该缓存操作修饰符标识其中要缓存与指令相关联的数据的并行高速缓存层级的级别; 并基于高速缓存操作修饰符实现高速缓存替换策略。

2. 发明授权

US07589741B1 Processing high numbers of independent textures in a 3-D graphics pipeline 有权
标题翻译：在3-D图形管线中处理大量独立纹理
公开(公告)号：US07589741B1
公开(公告)日：2009-09-15
申请号：US11736574
申请日：2007-04-17
申请人： Christopher D. S. Donham , Alexander L. Minkin
发明人： Christopher D. S. Donham , Alexander L. Minkin
IPC分类号： G09G5/00 , G06T11/40 , G06T1/00 , G06T15/50
CPC分类号： G06T1/20
摘要： Circuits, methods, and apparatus provide for the storage of texture descriptors in a graphics memory. Since the texture descriptors are stored in a graphics memory, they do not need to be stored in the graphics processor itself, thus reducing graphics processor circuitry and cost. This allows more textures to be associated with each graphics primitive, thereby improving image realism.
摘要翻译：电路，方法和装置提供了在图形存储器中存储纹理描述符。由于纹理描述符存储在图形存储器中，因此它们不需要存储在图形处理器本身中，从而减少图形处理器电路和成本。这允许更多的纹理与每个图形基元相关联，从而改善图像的真实性。

3. 发明授权

US07289126B1 Gamma-corrected texel storage in a graphics memory 有权
标题翻译： Gamma校正的纹理存储器存储在图形存储器中
公开(公告)号：US07289126B1
公开(公告)日：2007-10-30
申请号：US10445144
申请日：2003-05-23
申请人： Alexander L. Minkin , Harold Robert Feldman Zable , Matthew N. Papakipos
发明人： Alexander L. Minkin , Harold Robert Feldman Zable , Matthew N. Papakipos
IPC分类号： G09G5/00 , G06T15/50 , G06T15/00
CPC分类号： G09G5/363 , G06T11/001 , G06T15/005 , G09G2320/0276
摘要： Methods, circuits, and apparatus for handling gamma-corrected texels stored in a graphics memory. On-the-fly gamma-to-linear and linear-to-gamma conversions are performed such that gamma-corrected texels are provided to circuits that are able to process them, while linear valued texels are supplied where needed. In various embodiments, these conversions are done by lookup tables, software instructions, or dedicated hardware. Gamma-corrected texels may be tracked by a shader program, pipeline states, or driver instructions, and may be identified by header or flag information, or by part of a texture descriptor.
摘要翻译：用于处理存储在图形存储器中的伽马校正的纹素的方法，电路和装置。执行即时伽马对线性和线性到伽马转换，使得伽马校正的纹素提供给能够处理它们的电路，而在需要时提供线性值纹理。在各种实施例中，这些转换通过查找表，软件指令或专用硬件完成。伽马校正的纹素可以由着色器程序，流水线状态或驱动器指令来跟踪，并且可以由标题或标志信息或纹理描述符的一部分来标识。

4. 发明授权

US08266382B1 Cache interface protocol including arbitration and hints 有权
标题翻译：缓存接口协议包括仲裁和提示
公开(公告)号：US08266382B1
公开(公告)日：2012-09-11
申请号：US12650214
申请日：2009-12-30
申请人： Alexander L. Minkin , Steven J. Heinrich , Rajeshwaran Selvanesan , Charles McCarver , Stewart Glenn Carlton , Anjana Rajendran , Yan Yan Tang
发明人： Alexander L. Minkin , Steven J. Heinrich , Rajeshwaran Selvanesan , Charles McCarver , Stewart Glenn Carlton , Anjana Rajendran , Yan Yan Tang
IPC分类号： G06F13/00 , G06F13/28 , G06F3/00 , G06F5/00
CPC分类号： G06F13/28
摘要： One embodiment of the present invention sets forth a technique for arbitrating requests received from one of the multiple clients of an L1 cache and for providing hints to the client to assist in arbitration. The L1 cache services multiple clients with diverse latency and bandwidth requirements and may be reconfigured to provide memory spaces for clients executing multiple parallel threads, where the memory spaces each have a different scope.
摘要翻译：本发明的一个实施例提出了一种用于仲裁从L1高速缓存的多个客户机中的一个接收的请求并且向客户端提供帮助以协助仲裁的技术。 L1缓存服务于具有不同延迟和带宽需求的多个客户端，并且可以被重新配置为为执行多个并行线程的客户端提供存储空间，其中每个存储空间具有不同的范围。

5. 发明申请

US20110292065A1 RECONFIGURABLE DUAL TEXTURE PIPELINE WITH SHARED TEXTURE CACHE 有权
标题翻译：具有共享纹理高速缓存的可重构双纹道管道
公开(公告)号：US20110292065A1
公开(公告)日：2011-12-01
申请号：US13209444
申请日：2011-08-15
申请人： Alexander L. Minkin
发明人： Alexander L. Minkin
IPC分类号： G09G5/00
CPC分类号： G06T15/04 , G06T2200/28 , G06T2210/36
摘要： Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in an efficient manner. One such texture circuit can provide a configurable number of texel quads for a configurable number of pixels. For bilinear filtering, texels for a comparatively greater number of pixels can be retrieved. For trilinear filtering, texels in a first LOD are retrieved for a number of pixels during a first clock cycle, during a second clock cycle, texels in a second LOD are retrieved. When aniso filtering is needed, a greater number of texels can be retrieved for a comparatively lower number of pixels.
摘要翻译：提供纹理缓存和相关电路的电路，方法和装置，以有效的方式存储和检索纹素。一个这样的纹理电路可以为可配置数量的像素提供可配置数量的纹素四边形。对于双线性滤波，可以检索相对较大数量的像素的纹素。对于三线性滤波，在第一时钟周期期间，在第一时钟周期期间，针对多个像素检索第一LOD中的纹理，在第二个LOD中的纹理片段被检索。当需要进行aniso过滤时，可以为相对较少数量的像素检索更多数量的纹素。

6. 发明授权

US07999821B1 Reconfigurable dual texture pipeline with shared texture cache 有权
标题翻译：可重构双纹理管道与共享纹理缓存
公开(公告)号：US07999821B1
公开(公告)日：2011-08-16
申请号：US11960645
申请日：2007-12-19
申请人： Alexander L. Minkin
发明人： Alexander L. Minkin
IPC分类号： G09G5/00
CPC分类号： G06T15/04 , G06T2200/28 , G06T2210/36
摘要： Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in an efficient manner. One such texture circuit can provide a configurable number of texel quads for a configurable number of pixels. For bilinear filtering, texels for a comparatively greater number of pixels can be retrieved. For trilinear filtering, texels in a first LOD are retrieved for a number of pixels during a first clock cycle, during a second clock cycle, texels in a second LOD are retrieved. When aniso filtering is needed, a greater number of texels can be retrieved for a comparatively lower number of pixels.
摘要翻译：提供纹理缓存和相关电路的电路，方法和装置，以有效的方式存储和检索纹素。一个这样的纹理电路可以为可配置数量的像素提供可配置数量的纹素四边形。对于双线性滤波，可以检索相对较大数量的像素的纹素。对于三线性滤波，在第一时钟周期期间，在第一时钟周期期间，针对多个像素检索第一LOD中的纹理，在第二个LOD中的纹理片段被检索。当需要进行aniso过滤时，可以为相对较少数量的像素检索更多数量的纹素。

7. 发明申请

US20110082961A1 Sharing Data Crossbar for Reads and Writes in a Data Cache 有权
标题翻译：共享数据交叉开关用于在数据缓存中进行读写
公开(公告)号：US20110082961A1
公开(公告)日：2011-04-07
申请号：US12892862
申请日：2010-09-28
申请人： Alexander L. Minkin , Steven L. Heinrich , Rajeshwaran Selvanesan , Stewart Glenn Carlton , John R. Nickolls
发明人： Alexander L. Minkin , Steven L. Heinrich , Rajeshwaran Selvanesan , Stewart Glenn Carlton , John R. Nickolls
IPC分类号： G06F13/36 , G06F13/00
CPC分类号： G06F13/4022 , G06F13/4031
摘要： The invention sets forth an L1 cache architecture that includes a crossbar unit configured to transmit data associated with both read data requests and write data requests. Data associated with read data requests is retrieved from a cache memory and transmitted to the client subsystems. Similarly, data associated with write data requests is transmitted from the client subsystems to the cache memory. To allow for the transmission of both read and write data on the crossbar unit, an arbiter is configured to schedule the crossbar unit transmissions as well and arbitrate between data requests received from the client subsystems.
摘要翻译：本发明提出了一种L1缓存架构，其包括被配置为发送与读取数据请求和写入数据请求相关联的数据的交叉单元。与读取数据请求相关联的数据从高速缓冲存储器检索并发送到客户机子系统。类似地，与写数据请求相关联的数据从客户端子系统发送到高速缓冲存储器。为了允许在交叉开关单元上传输读取和写入数据，仲裁器被配置为调度交叉单元传输以及在从客户端子系统接收的数据请求之间进行仲裁。

8. 发明授权

US09286256B2 Sharing data crossbar for reads and writes in a data cache 有权
标题翻译：在数据高速缓存中共享用于读写数据的交叉开关
公开(公告)号：US09286256B2
公开(公告)日：2016-03-15
申请号：US12892862
申请日：2010-09-28
申请人： Alexander L. Minkin , Steven J. Heinrich , Rajeshwaran Selvanesan , Stewart Glenn Carlton , John R. Nickolls
发明人： Alexander L. Minkin , Steven J. Heinrich , Rajeshwaran Selvanesan , Stewart Glenn Carlton , John R. Nickolls
IPC分类号： G06F12/00 , G06F13/40 , G06F13/00 , G06F13/28
CPC分类号： G06F13/4022 , G06F13/4031
摘要： The invention sets forth an L1 cache architecture that includes a crossbar unit configured to transmit data associated with both read data requests and write data requests. Data associated with read data requests is retrieved from a cache memory and transmitted to the client subsystems. Similarly, data associated with write data requests is transmitted from the client subsystems to the cache memory. To allow for the transmission of both read and write data on the crossbar unit, an arbiter is configured to schedule the crossbar unit transmissions as well and arbitrate between data requests received from the client subsystems.
摘要翻译：本发明提出了一种L1缓存架构，其包括被配置为发送与读取数据请求和写入数据请求相关联的数据的交叉单元。与读取数据请求相关联的数据从高速缓冲存储器检索并发送到客户机子系统。类似地，与写数据请求相关联的数据从客户端子系统发送到高速缓冲存储器。为了允许在交叉开关单元上传输读取和写入数据，仲裁器被配置为调度交叉单元传输以及在从客户端子系统接收的数据请求之间进行仲裁。

9. 发明授权

US08217954B2 Reconfigurable dual texture pipeline with shared texture cache 有权
标题翻译：可重构双纹理管道与共享纹理缓存
公开(公告)号：US08217954B2
公开(公告)日：2012-07-10
申请号：US13209444
申请日：2011-08-15
申请人： Alexander L. Minkin
发明人： Alexander L. Minkin
IPC分类号： G09G5/00
CPC分类号： G06T15/04 , G06T2200/28 , G06T2210/36
摘要： Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in an efficient manner. One such texture circuit can provide a configurable number of texel quads for a configurable number of pixels. For bilinear filtering, texels for a comparatively greater number of pixels can be retrieved. For trilinear filtering, texels in a first LOD are retrieved for a number of pixels during a first clock cycle, during a second clock cycle, texels in a second LOD are retrieved. When aniso filtering is needed, a greater number of texels can be retrieved for a comparatively lower number of pixels.
摘要翻译：提供纹理缓存和相关电路的电路，方法和装置，以有效的方式存储和检索纹素。一个这样的纹理电路可以为可配置数量的像素提供可配置数量的纹素四边形。对于双线性滤波，可以检索相对较大数量的像素的纹素。对于三线性滤波，在第一时钟周期期间，在第一时钟周期期间，针对多个像素检索第一LOD中的纹理，在第二个LOD中的纹理片段被检索。当需要进行aniso过滤时，可以为相对较少数量的像素检索更多数量的纹素。

10. 发明授权

US07948498B1 Efficient texture state cache 有权
标题翻译：高效的纹理状态缓存
公开(公告)号：US07948498B1
公开(公告)日：2011-05-24
申请号：US11549566
申请日：2006-10-13
申请人： Alexander L. Minkin
发明人： Alexander L. Minkin
IPC分类号： G06T11/40
CPC分类号： G06T11/40 , G06T1/60 , G06T15/04
摘要： Circuits, methods, and apparatus that store a large number of texture states in an efficient manner. A level-one texture cache includes cache lines that are distributed throughout a texture pipeline, where each cache line stores a texture state. The cache lines can be updated by retrieving data from a second-level texture state cache, which in turn is updated from a frame buffer or graphics memory. The second-level texture state cache can prefetch texture states using a list of textures that are needed for a shader program or program portion.
摘要翻译：以有效的方式存储大量纹理状态的电路，方法和装置。一级纹理缓存包括分布在纹理流水线中的高速缓存行，其中每个高速缓存行存储纹理状态。可以通过从第二级纹理状态高速缓存中检索数据来更新高速缓存行，该缓存行又从帧缓冲器或图形存储器更新。第二级纹理状态缓存可以使用着色器程序或程序部分所需的纹理列表来预取纹理状态。

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