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1. 发明授权

US07861106B2 Hierarchical configurations in error-correcting computer systems 失效
标题翻译：纠错计算机系统中的分层配置
公开(公告)号：US07861106B2
公开(公告)日：2010-12-28
申请号：US11506455
申请日：2006-08-18
申请人： Algirdas Avizienis
发明人： Algirdas Avizienis
IPC分类号： G06F11/00
CPC分类号： G06F11/0793
摘要： When errors arise in a computing system that has plural modules, this invention corrects those errors. In the first instance, the invention excludes the computing system itself, but receives error messages from the plural modules of that system—along plural receiving connections, respectively. Plural sending connections return corrective responses to plural modules of that system, respectively. In a second instance, the invention further incorporates that system. The invention is hierarchical: plural levels or tiers of apparatus and function are present—a first (typically uppermost) one directly serving that system as described above, and others (lower) that analogously serve the first tier of the invention—and then also the subsequent tiers, in a cascading or nested fashion, down to preferably a bottom-level tier supporting all the upper ones. Each level preferably controls power interruption and restoration to higher levels. Ideally the hierarchy is in the form of a “system on chip”.
摘要翻译：当在具有多个模块的计算系统中出现错误时，本发明校正了这些错误。在第一种情况下，本发明排除了计算系统本身，而是分别从多个接收连接的系统的多个模块接收错误消息。多个发送连接分别返回对该系统的多个模块的纠正响应。在第二种情况下，本发明还包括该系统。本发明是分级的：存在多个级别或多级的装置和功能 - 如上所述直接服务于该系统的第一（通常是最上面的）和类似地用于本发明的第一层的其他（较低），然后也是随后的级联，以级联或嵌套的方式，最好是支持所有上层的底层。每个级别优选地将电源中断和恢复控制到更高级别。理想情况下，层次结构是“芯片上系统”的形式。

2. 发明申请

US20100218035A1 Self-testing and -repairing fault-tolerance infrastructure for computer systems 审中-公开
标题翻译：计算机系统的自检和修复容错基础设施
公开(公告)号：US20100218035A1
公开(公告)日：2010-08-26
申请号：US12655511
申请日：2009-12-31
申请人： Algirdas Avizienis
发明人： Algirdas Avizienis
IPC分类号： G06F11/20
CPC分类号： G06F11/2028 , G06F11/183
摘要： ASICs or like fabrication-preprogrammed hardware provide controlled power and recovery signals to a computing system that is made up of commercial, off-the-shelf components—and that has its own conventional hardware and software fault-protection systems, but these are vulnerable to failure due to external and internal events, bugs, human malice and operator error. The computing system preferably includes processors and programming that are diverse in design and source. The hardware infrastructure uses triple modular redundancy to test itself as well as the computing system, and to remove failed elements—powering up and loading data into spares. The hardware is very simplified in design and programs, so that bugs can be thoroughly rooted out. Communications between the protected system and the hardware are protected by very simple circuits with duplex redundancy.
摘要翻译： ASIC或类似制造预编程硬件向由商业的现成组件组成的计算系统提供受控的功率和恢复信号，并且具有其自己的常规硬件和软件故障保护系统，但是这些容易受到由于外部和内部事件，错误，人类恶意和操作员错误导致的故障。计算系统优选地包括设计和来源不同的处理器和编程。硬件基础架构使用三重模块化冗余来测试自身以及计算系统，并删除故障元素 - 启动并将数据加载到备件中。硬件设计和程序非常简化，可以彻底根除错误。受保护系统和硬件之间的通信由具有双工冗余的非常简单的电路保护。

3. 发明申请

US20110252268A1 Hierarchical configurations in error-correcting computer systems 审中-公开
标题翻译：纠错计算机系统中的分层配置
公开(公告)号：US20110252268A1
公开(公告)日：2011-10-13
申请号：US12928557
申请日：2010-12-14
申请人： Algirdas Avizienis
发明人： Algirdas Avizienis
IPC分类号： G06F11/07
CPC分类号： G06F11/0793
摘要： When errors arise in a computing system that has plural modules, this invention corrects those errors. In the first instance, the invention excludes the computing system itself, but receives error messages from the plural modules of that system—along plural receiving connections, respectively. Plural sending connections return corrective responses to plural modules of that system, respectively. In a second instance, the invention further incorporates that system. The invention is hierarchical: plural levels or tiers of apparatus and function are present—a first (typically uppermost) one directly serving that system as described above, and others (lower) that analogously serve the first tier of the invention—and than also the subsequent tiers, in a cascading or nested fashion, down to preferably a bottom-level tier supporting all the upper ones. Each level preferably controls power interruption and restoration to higher levels. Ideally the hierarchy is in the form of a “system on chip”.
摘要翻译：当在具有多个模块的计算系统中出现错误时，本发明校正了这些错误。在第一种情况下，本发明排除了计算系统本身，而是分别从多个接收连接的系统的多个模块接收错误消息。多个发送连接分别返回对该系统的多个模块的纠正响应。在第二种情况下，本发明还包括该系统。本发明是分级的：存在多个级别或多级的装置和功能 - 如上所述直接服务于该系统的第一（通常是最上面的）和类似地用于本发明的第一层的其他（较低），而且还随后的级联，以级联或嵌套的方式，最好是支持所有上层的底层。每个级别优选地将电源中断和恢复控制到更高级别。理想情况下，层次结构是“芯片上系统”的形式。

4. 发明授权

US07908520B2 Self-testing and -repairing fault-tolerance infrastructure for computer systems 失效
标题翻译：计算机系统的自检和修复容错基础设施
公开(公告)号：US07908520B2
公开(公告)日：2011-03-15
申请号：US09886959
申请日：2001-06-20
申请人： Algirdas Avizienis
发明人： Algirdas Avizienis
IPC分类号： G06F11/00
CPC分类号： G06F11/2028 , G06F11/183
摘要： ASICs or like fabrication-preprogrammed hardware provide controlled power and recovery signals to a computing system that is made up of commercial, off-the-shelf components—and that has its own conventional hardware and software fault-protection systems, but these are vulnerable to failure due to external and internal events, bugs, human malice and operator error. The computing system preferably includes processors and programming that are diverse in design and source. The hardware infrastructure uses triple modular redundancy to test itself as well as the computing system, and to remove failed elements—powering up and loading data into spares. The hardware is very simplified in design and programs, so that bugs can be thoroughly rooted out. Communications between the protected system and the hardware are protected by very simple circuits with duplex redundancy.
摘要翻译： ASIC或类似制造预编程硬件向由商业的现成组件组成的计算系统提供受控的功率和恢复信号，并且具有其自己的常规硬件和软件故障保护系统，但是这些容易受到由于外部和内部事件，错误，人类恶意和操作员错误导致的故障。计算系统优选地包括设计和来源不同的处理器和编程。硬件基础架构使用三重模块化冗余来测试自身以及计算系统，并删除故障元素 - 启动并将数据加载到备件中。硬件设计和程序非常简化，可以彻底根除错误。受保护系统和硬件之间的通信由具有双工冗余的非常简单的电路保护。

5. 发明申请

US20070067673A1 Hierarchical configurations in error-correcting computer systems 失效
标题翻译：纠错计算机系统中的分层配置
公开(公告)号：US20070067673A1
公开(公告)日：2007-03-22
申请号：US11506455
申请日：2006-08-18
申请人： Algirdas Avizienis
发明人： Algirdas Avizienis
IPC分类号： G06F11/00
CPC分类号： G06F11/0793
摘要： When errors arise in a computing system that has plural modules, this invention corrects those errors. In the first instance, the invention excludes the computing system itself, but receives error messages from the plural modules of that system—along plural receiving connections, respectively. Plural sending connections return corrective responses to plural modules of that system, respectively. In a second instance, the invention further incorporates that system. The invention is hierarchical: plural levels or tiers of apparatus and function are present—a first (typically uppermost) one directly serving that system as described above, and others (lower) that analogously serve the first tier of the invention—and then also the subsequent tiers, in a cascading or nested fashion, down to preferably a bottom-level tier supporting all the upper ones. Each level preferably controls power interruption and restoration to higher levels. Ideally the hierarchy is in the form of a “system on chip”.
摘要翻译：当在具有多个模块的计算系统中出现错误时，本发明校正了这些错误。在第一种情况下，本发明排除了计算系统本身，而是分别从多个接收连接的系统的多个模块接收错误消息。多个发送连接分别返回对该系统的多个模块的纠正响应。在第二种情况下，本发明还包括该系统。本发明是分级的：存在多个级别或多级的装置和功能 - 如上所述直接服务于该系统的第一（通常是最上面的）和类似地用于本发明的第一层的其他（较低），然后也是随后的级联，以级联或嵌套的方式，最好是支持所有上层的底层。每个级别优选地将电源中断和恢复控制到更高级别。理想情况下，层次结构是“芯片上系统”的形式。

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