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1. 发明授权

US08930790B1 Method and apparatus for identifying selected values from among a set of values 有权
标题翻译：用于从一组值中识别所选值的方法和装置
公开(公告)号：US08930790B1
公开(公告)日：2015-01-06
申请号：US14027081
申请日：2013-09-13
申请人： Antcor S.A.
发明人： Ioannis Tsatsaragkos , Nikolaos L. Kanistras , Vassilis Paliouras
IPC分类号： H03M13/00 , G06F11/07 , H03M13/11
CPC分类号： G06F11/0751 , H03M13/1102 , H03M13/112 , H03M13/1122 , H03M13/6502 , H03M13/6572 , H03M13/658
摘要： The present invention is directed toward identifying selected values from among a set of values. In accordance with an embodiment, a method of identifying two selected values from among a plurality of values comprises: partitioning the plurality of values into pairs of values; for each pair of values, using a comparator to select one of the two values to form a vector from the selected value of each pair; and applying the vector to a hardware unit that identifies first and second extreme values from among the values of the vector.
摘要翻译：本发明旨在从一组值中识别所选择的值。根据实施例，从多个值中识别两个选择的值的方法包括：将所述多个值分成多对值; 对于每对值，使用比较器从两个值的选择值中选择两个值中的一个来形成向量; 以及将所述向量应用于从所述向量的值中识别第一和第二极值的硬件单元。

2. 发明申请

US20150082112A1 LOW DENSITY PARITY CHECK ENCODER AND ENCODING METHOD 有权
标题翻译：低密度奇偶校验编码器和编码方法
公开(公告)号：US20150082112A1
公开(公告)日：2015-03-19
申请号：US14031505
申请日：2013-09-19
申请人： Antcor S.A.
发明人： Ahmed S. Mahdi , Nikolaos L. Kanistras , Vassilis Paliouras
IPC分类号： H03M13/11
CPC分类号： H03M13/1102 , H03M13/1148 , H03M13/116 , H03M13/13 , H03M13/611 , H03M13/618 , H03M13/6362 , H03M13/6502 , H03M13/6516 , H03M13/6527 , H03M13/6572
摘要： The present invention is directed toward a parity check encoder for low density error correction codes and to an encoding method. In accordance with an embodiment, an encoder for error correction coding comprises: first hardware resources configured to receive a message bits vector and to compute an intermediate parity bits vector from the message bits vector wherein the intermediate parity bits vector is computed based on a sub-matrix of a parity check matrix; and second hardware resources configured to compute a parity bits vector from the intermediate parity bits vector, wherein the second hardware resources are configured to compute parity bits for multiple different codes, and wherein portions of the hardware resources that are configured to compute the parity bits for a particular one of the codes are commonly shared with portions of the hardware resources that are configured to compute the parity bits for another particular one of the codes.
摘要翻译：本发明涉及用于低密度纠错码的奇偶校验编码器和编码方法。根据实施例，用于纠错编码的编码器包括：第一硬件资源，被配置为从消息比特向量接收消息比特向量并计算中间奇偶校验位向量，其中基于子帧向量计算中间奇偶校验位向量，奇偶校验矩阵的矩阵; 以及第二硬件资源，被配置为从所述中间奇偶校验位向量计算奇偶校验位向量，其中所述第二硬件资源被配置为针对多个不同的代码计算奇偶校验位，并且其中所述硬件资源的被配置为计算奇偶校验位的部分所述代码中的特定一个通常与被配置为为另一特定代码计算奇偶校验位的硬件资源的部分共享。

3. 发明授权

US09003257B1 Low density parity check encoder and encoding method 有权
标题翻译：低密度奇偶校验编码器和编码方法
公开(公告)号：US09003257B1
公开(公告)日：2015-04-07
申请号：US14031505
申请日：2013-09-19
申请人： Antcor S.A.
发明人： Ahmed S Mahdi , Nikolaos L Kanistras , Vassilis Paliouras
IPC分类号： H03M13/00 , H03M13/11
CPC分类号： H03M13/1102 , H03M13/1148 , H03M13/116 , H03M13/13 , H03M13/611 , H03M13/618 , H03M13/6362 , H03M13/6502 , H03M13/6516 , H03M13/6527 , H03M13/6572
摘要： The present invention is directed toward a parity check encoder for low density error correction codes and to an encoding method. In accordance with an embodiment, an encoder for error correction coding comprises: first hardware resources configured to receive a message bits vector and to compute an intermediate parity bits vector from the message bits vector wherein the intermediate parity bits vector is computed based on a sub-matrix of a parity check matrix; and second hardware resources configured to compute a parity bits vector from the intermediate parity bits vector, wherein the second hardware resources are configured to compute parity bits for multiple different codes, and wherein portions of the hardware resources that are configured to compute the parity bits for a particular one of the codes are commonly shared with portions of the hardware resources that are configured to compute the parity bits for another particular one of the codes.
摘要翻译：本发明涉及用于低密度纠错码的奇偶校验编码器和编码方法。根据实施例，用于纠错编码的编码器包括：第一硬件资源，被配置为从消息比特向量接收消息比特向量并计算中间奇偶校验位向量，其中基于子帧向量计算中间奇偶校验位向量，奇偶校验矩阵的矩阵; 以及第二硬件资源，被配置为从所述中间奇偶校验位向量计算奇偶校验位向量，其中所述第二硬件资源被配置为针对多个不同的代码计算奇偶校验位，并且其中所述硬件资源的被配置为计算奇偶校验位的部分所述代码中的特定一个通常与被配置为为另一特定代码计算奇偶校验位的硬件资源的部分共享。

4. 发明授权

US08804804B1 Estimation and compensation for carrier frequency offset and sampling clock offset in a communication system 有权
标题翻译：通信系统中载波频率偏移和采样时钟偏移的估计和补偿
公开(公告)号：US08804804B1
公开(公告)日：2014-08-12
申请号：US13852376
申请日：2013-03-28
申请人： Antcor S.A.
发明人： Ioannis Sarris
IPC分类号： H03H7/30 , H03H7/40 , H04L7/00
CPC分类号： H04L27/2695 , H04L27/2657 , H04L27/2663 , H04L27/2672 , H04L27/2675
摘要： A system for estimating clock frequency offset and sampling clock offset in a communication system is provided. A receiver is configured to receive a communication signal having been transmitted from a transmitter via a communication channel. The receiver has a signal processor, wherein the signal processor is configured to generate an estimate of a carrier frequency offset and an estimate of a sampling clock offset from the received communication signal by: extracting a vector of pilot symbols from the received signal; performing equalization on the pilot symbols; performing clock frequency offset and sampling clock offset compensation on the pilot symbols; generating the estimate of a carrier frequency offset by estimating a common phase rotation using a first Taylor series approximation; and generating the estimate of the sampling clock offset by estimating phase differences between pairs of pilot symbols using a second Taylor series approximation.
摘要翻译：提供了一种用于估计通信系统中的时钟频率偏移和采样时钟偏移的系统。接收机被配置为接收经由通信信道从发射机发送的通信信号。所述接收机具有信号处理器，其中，所述信号处理器被配置为通过以下方式从接收到的信号中提取导频符号的向量来产生载波频率偏移的估计和对所接收的通信信号的采样时钟偏移的估计; 对导频符号执行均衡; 对导频符号执行时钟频率偏移和采样时钟偏移补偿; 通过使用第一泰勒级数近似来估计公共相位旋转来产生载波频率偏移的估计; 以及通过使用第二泰勒级数逼近来估计导频符号对之间的相位差来生成采样时钟偏移的估计。

5. 发明授权

US08713399B1 Reconfigurable barrel shifter and rotator 有权
标题翻译：可重构桶形移位器和旋转器
公开(公告)号：US08713399B1
公开(公告)日：2014-04-29
申请号：US14051144
申请日：2013-10-10
申请人： Antcor S.A.
发明人： Ioannis Tsatsaragkos , Vassilis Paliouras
IPC分类号： H03M13/00
CPC分类号： H03M13/6527 , H03M13/1111 , H03M13/116 , H03M13/6516
摘要： The present invention is directed toward reconfigurable barrel shifters and rotators. A barrel shifter comprises an array of multiplexers, the array having a plurality of inputs and a plurality of outputs and wherein the array of multiplexers is configured to rotate a set of n input messages applied to the inputs by a selected number of positions at the outputs and wherein the number n of messages contained in the set is selectable from among a plurality of values, by changing only select control signal inputs to the array of multiplexers.
摘要翻译：本发明涉及可重构桶形移位器和转子。桶形移位器包括多路复用器阵列，阵列具有多个输入和多个输出，并且其中多路复用器阵列被配置为将施加到输入的一组n个输入消息旋转在输出处的选定数量的位置并且其中，通过仅将多路复用器阵列的选择控制信号输入改变，可以从多个值中选择集合中包含的消息数n。

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