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1. 发明授权

US08918988B2 Methods for controlling wafer curvature 有权
标题翻译：控制晶片曲率的方法
公开(公告)号：US08918988B2
公开(公告)日：2014-12-30
申请号：US13604820
申请日：2012-09-06
申请人： Mohammed Fazil Fayaz , Jeffery Burton Maxson , Anthony Kendall Stamper , Daniel Scott Vanslette
发明人： Mohammed Fazil Fayaz , Jeffery Burton Maxson , Anthony Kendall Stamper , Daniel Scott Vanslette
IPC分类号： H05K3/30 , H01L23/522 , H01L23/31 , H01L21/768 , H01L23/00
CPC分类号： H01L23/522 , H01L21/76801 , H01L23/3157 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05572 , H01L2224/13022 , H01L2224/131 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01019 , H01L2924/1305 , H01L2924/14 , H01L2924/3511 , Y10S438/925 , Y10T29/49002 , Y10T29/49117 , Y10T29/49124 , Y10T29/4913 , Y10T29/49135 , Y10T29/49151 , Y10T29/49156 , Y10T29/49167 , H01L2924/014 , H01L2224/13099 , H01L2924/00 , H01L2224/05552
摘要： Methods and structures for controlling wafer curvature during fabrication of integrated circuits caused by stressed films. The methods include controlling the conductor density of wiring levels, adding compensating stressed film layers and disturbing the continuity of stress films with the immediately lower layer. The structure includes integrated circuits having compensating stressed film layers.
摘要翻译：由应力膜引起的集成电路制造期间控制晶片曲率的方法和结构。这些方法包括控制布线电平的导体密度，增加补偿应力薄膜层，并使紧密的下层干扰应力薄膜的连续性。该结构包括具有补偿应力膜层的集成电路。

2. 发明授权

US08518787B2 Through wafer vias and method of making same 有权
标题翻译：通过晶圆通孔及其制作方法
公开(公告)号：US08518787B2
公开(公告)日：2013-08-27
申请号：US13604731
申请日：2012-09-06
申请人： Hanyi Ding , Alvin Jose Joseph , Anthony Kendall Stamper
发明人： Hanyi Ding , Alvin Jose Joseph , Anthony Kendall Stamper
IPC分类号： H01L21/763
CPC分类号： H01L21/76898 , H01L21/6835 , H01L21/823475 , H01L21/823481 , H01L23/481 , H01L23/66 , H01L24/05 , H01L24/10 , H01L24/12 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2221/68372 , H01L2223/6616 , H01L2224/0401 , H01L2224/0557 , H01L2224/13 , H01L2224/13025 , H01L2224/13099 , H01L2224/2518 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/0105 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/00 , H01L2224/05552
摘要： A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.
摘要翻译：用于通过晶片通孔形成和结构的方法，所述晶片通孔和通过晶片通孔形成的信号传输线。通过晶片通孔形成的方法包括通过半导体衬底形成贯穿晶片通孔的阵列，其包括至少一个导电晶片通孔和至少一个不导电的晶片通孔，该半导体衬底具有顶表面和相对的底表面通过晶片通孔从衬底的顶表面延伸到衬底的底表面的通过晶片通孔的阵列。

3. 发明授权

US08052799B2 By-product collecting processes for cleaning processes 有权
标题翻译：用于清洁过程的副产品收集过程
公开(公告)号：US08052799B2
公开(公告)日：2011-11-08
申请号：US11548717
申请日：2006-10-12
申请人： Edward Crandal Cooney, III , William Joseph Murphy , Anthony Kendall Stamper , David Craig Strippe
发明人： Edward Crandal Cooney, III , William Joseph Murphy , Anthony Kendall Stamper , David Craig Strippe
IPC分类号： C23F1/00 , H01L21/02 , B08B17/02
CPC分类号： H01L21/67028 , H01J37/3244 , H01J37/32862 , H01L21/02063
摘要： An apparatus and a method for operating the same. The method includes providing an apparatus which includes a chamber, wherein the chamber includes first and second inlets, an anode and a cathode structures in the chamber, and a wafer on the cathode structure. A cleaning gas is injected into the chamber via the first inlet. A collecting gas is injected into the chamber via the second inlet. The cleaning gas when ionized has a property of etching a top surface of the wafer resulting in a by-product mixture in the chamber. The collecting gas has a property of preventing the by-product mixture from depositing back to the surface of the wafer.
摘要翻译：一种装置及其操作方法。该方法包括提供一种包括腔室的装置，其中腔室包括第一和第二入口，腔室中的阳极和阴极结构以及阴极结构上的晶片。清洁气体经由第一入口注入腔室。收集气体经由第二入口注入到腔室中。电离时的清洁气体具有腐蚀晶片的顶面的特性，导致室中的副产物混合物。收集气体具有防止副产物混合物沉积回晶片表面的性质。

4. 发明授权

US08013342B2 Double-sided integrated circuit chips 有权
标题翻译：双面集成电路芯片
公开(公告)号：US08013342B2
公开(公告)日：2011-09-06
申请号：US11939612
申请日：2007-11-14
申请人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
IPC分类号： H01L29/04
CPC分类号： G06F17/5077 , H01L21/6835 , H01L21/76895 , H01L21/84 , H01L23/481 , H01L23/535 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L29/045 , H01L2221/6835 , H01L2221/68359 , H01L2221/68368 , H01L2224/83894 , H01L2224/9202 , H01L2225/06513 , H01L2924/01019 , H01L2924/01029 , H01L2924/0132 , H01L2924/1305 , H01L2924/14 , H01L2924/19041 , H01L2924/01007 , H01L2924/01022 , H01L2924/00
摘要： A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
摘要翻译：双面集成电路芯片，制造双面集成电路芯片的方法和双面集成电路芯片的设计结构。该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。下晶片可以包括布线水平。下部晶片可以包括用于触点的着陆焊盘。与下晶片的硅层的接触可以被硅化。

5. 发明授权

US07960245B2 Dual wired integrated circuit chips 有权
公开(公告)号：US07960245B2
公开(公告)日：2011-06-14
申请号：US12029575
申请日：2008-02-12
申请人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Anthony Kendall Stamper
IPC分类号： H01L21/30
CPC分类号： H01L21/76898 , H01L21/84 , H01L23/481 , H01L23/522 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

6. 发明申请

US20110129996A1 THROUGH SUBSTRATE ANNULAR VIA INCLUDING PLUG FILLER 审中-公开
标题翻译：通过包括插入式灌装机在内的基板
公开(公告)号：US20110129996A1
公开(公告)日：2011-06-02
申请号：US13025678
申请日：2011-02-11
申请人： Peter James Lindgren , Edmund Juris Sprogis , Anthony Kendall Stamper , Kenneth Jay Stein
发明人： Peter James Lindgren , Edmund Juris Sprogis , Anthony Kendall Stamper , Kenneth Jay Stein
IPC分类号： H01L21/28
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer.
摘要翻译：贯通基板通孔包括在通孔基板孔周边的环形导体层和被环形导体层围绕的塞子层。一种用于制造贯通衬底通孔的方法，包括在衬底内形成盲孔，并在盲孔内依次形成并随后在盲孔内进行平面化，该保形导体层不填充填充孔的孔和塞层。然后可以将衬底的背面平坦化以至少露出平坦化的共形导体层。

7. 发明申请

US20110049723A1 METHODS AND STRUCTURES FOR CONTROLLING WAFER CURVATURE 有权
标题翻译：控制波形曲线的方法和结构
公开(公告)号：US20110049723A1
公开(公告)日：2011-03-03
申请号：US12547566
申请日：2009-08-26
申请人： Mohammed Fazil Fayaz , Jeffery Burton Maxson , Anthony Kendall Stamper , Daniel Scott Vanslette
发明人： Mohammed Fazil Fayaz , Jeffery Burton Maxson , Anthony Kendall Stamper , Daniel Scott Vanslette
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/522 , H01L21/76801 , H01L23/3157 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05572 , H01L2224/13022 , H01L2224/131 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01019 , H01L2924/1305 , H01L2924/14 , H01L2924/3511 , Y10S438/925 , Y10T29/49002 , Y10T29/49117 , Y10T29/49124 , Y10T29/4913 , Y10T29/49135 , Y10T29/49151 , Y10T29/49156 , Y10T29/49167 , H01L2924/014 , H01L2224/13099 , H01L2924/00 , H01L2224/05552
摘要： Methods and structures for controlling wafer curvature during fabrication of integrated circuits caused by stressed films. The methods include controlling the conductor density of wiring levels, adding compensating stressed film layers and disturbing the continuity of stress films with the immediately lower layer. The structure includes integrated circuits having compensating stressed film layers.
摘要翻译：由应力膜引起的集成电路制造期间控制晶片曲率的方法和结构。这些方法包括控制布线电平的导体密度，增加补偿应力薄膜层，并使紧密的下层干扰应力薄膜的连续性。该结构包括具有补偿应力膜层的集成电路。

8. 发明授权

US07861204B2 Structures including integrated circuits for reducing electromigration effect 有权
标题翻译：包括用于降低电迁移效应的集成电路的结构
公开(公告)号：US07861204B2
公开(公告)日：2010-12-28
申请号：US11960853
申请日：2007-12-20
申请人： Anthony Kendall Stamper , Timothy Dooling Sullivan , Ping-Chuan Wang
发明人： Anthony Kendall Stamper , Timothy Dooling Sullivan , Ping-Chuan Wang
IPC分类号： G06F17/50
CPC分类号： H01L23/53223 , H01L23/528 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A design structure including an integrated circuit for reducing the electromigration effect. The IC includes a substrate and a power transistor which has first and second source/drain regions. The IC further includes first, second, and third electrically conductive line segments being (i) directly above the first source/drain region and (ii) electrically coupled to the first source/drain region through first contact regions and second contact regions, respectively. The first and second electrically conductive line segments (i) reside in a first interconnect layer of the integrated circuit and (ii) run in the reference direction. The IC further includes an electrically conductive line being (i) directly above the first source/drain region, (ii) electrically coupled to the first and second electrically conductive line segments through a first via and a second via, respectively, (iii) resides in a second interconnect layer of the integrated circuit, and (iv) runs in the reference direction.
摘要翻译：一种设计结构，包括用于降低电迁移效应的集成电路。 IC包括具有第一和第二源/漏区的衬底和功率晶体管。 IC还包括第一，第二和第三导电线段，其直接在第一源极/漏极区域的上方，以及（ii）分别通过第一接触区域和第二接触区域电耦合到第一源极/漏极区域。第一和第二导电线段（i）驻留在集成电路的第一互连层中，并且（ii）沿参考方向延伸。 IC还包括导电线，其是（i）直接在第一源极/漏极区域上方，（ii）分别通过第一通孔和第二通孔电耦合到第一和第二导电线段，（iii）驻留在集成电路的第二互连层中，以及（iv）在参考方向上延伸。

9. 发明授权

US07851923B2 Low resistance and inductance backside through vias and methods of fabricating same 有权
标题翻译：低电阻和电感背面穿过通孔及其制造方法
公开(公告)号：US07851923B2
公开(公告)日：2010-12-14
申请号：US12410728
申请日：2009-03-25
申请人： Mete Erturk , Robert A. Groves , Jeffrey Bowman Johnson , Alvin Jose Joseph , Qizhi Liu , Edmund Juris Sprogis , Anthony Kendall Stamper
发明人： Mete Erturk , Robert A. Groves , Jeffrey Bowman Johnson , Alvin Jose Joseph , Qizhi Liu , Edmund Juris Sprogis , Anthony Kendall Stamper
IPC分类号： H01L23/48
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.
摘要翻译：背面接触结构及其制造方法。该方法包括：在衬底中形成电介质隔离，所述衬底具有前侧和相对的背面; 在所述基板的前侧形成第一电介质层; 在所述第一电介质层中形成沟槽，所述沟槽在所述电介质隔离的周边内并且在所述介电隔离的周边内对准并且延伸到所述电介质隔将形成在第一电介质层中的沟槽通过电介质隔离延伸到衬底中至小于衬底厚度的深度; 填充沟槽并将沟槽的顶表面与第一介电层的顶表面共平面化以形成导电通孔; 并从衬底的背面稀释衬底以露出通孔。

10. 发明授权

US07732294B2 Post last wiring level inductor using patterned plate process 失效
标题翻译：使用图案板工艺后最后布线级电感器
公开(公告)号：US07732294B2
公开(公告)日：2010-06-08
申请号：US12170464
申请日：2008-07-10
申请人： Anil Kumar Chinthakindi , Douglas Duane Coolbaugh , John Edward Florkey , Jeffrey Peter Gambino , Zhong-Xiang He , Anthony Kendall Stamper , Kunal Vaed
发明人： Anil Kumar Chinthakindi , Douglas Duane Coolbaugh , John Edward Florkey , Jeffrey Peter Gambino , Zhong-Xiang He , Anthony Kendall Stamper , Kunal Vaed
IPC分类号： H01L21/20
CPC分类号： H01L21/76885 , H01L21/76804 , H01L21/76807 , H01L21/76808 , H01L21/76814 , H01L21/76834 , H01L21/76852 , H01L21/76865 , H01L21/76879 , H01L23/5227 , H01L23/53238 , H01L28/10 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： A method of a semiconductor device. A substrate is provided. At least one metal wiring level is within the substrate. An insulative layer is deposited on a surface of the substrate. An inductor is formed within the insulative layer using a patterned plate process. A wire bond pad is formed within the insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.
摘要翻译：一种半导体器件的方法。提供基板。衬底内至少有一个金属布线层。绝缘层沉积在衬底的表面上。使用图案化板工艺在绝缘层内形成电感器。在绝缘层内形成引线接合焊盘，其中引线接合焊盘的至少一部分与电感器基本上共面。

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