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1. 发明申请

US20130010554A1 SEMICONDUCTOR MEMORY DEVICE, METHOD OF CONTROLLING READ PREAMBLE SIGNAL THEREOF, AND DATA TRANSMISSION SYSTEM 有权
公开(公告)号：US20130010554A1
公开(公告)日：2013-01-10
申请号：US13621061
申请日：2012-09-15
申请人： Atsuo KOSHIZUKA
发明人： Atsuo KOSHIZUKA
IPC分类号： G11C7/22
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C15/00 , G11C15/04
摘要： A system, includes a controller comprising a plurality of first external terminals configured to supply a command and an address, and communicate a data, and communicate a strobe signal related to the data; and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, at least one of the plurality of first external terminals and at least one of the plurality of second external terminals each being capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data between the controller and the semiconductor memory device, the semiconductor memory device further including a preamble register configured to be capable of storing the information.

2. 发明申请

US20120269023A1 SYSTEM WITH CONTROLLER AND MEMORY 有权
标题翻译：具有控制器和存储器的系统
公开(公告)号：US20120269023A1
公开(公告)日：2012-10-25
申请号：US13488602
申请日：2012-06-05
申请人： Atsuo KOSHIZUKA
发明人： Atsuo KOSHIZUKA
IPC分类号： G11C8/18
CPC分类号： G11C7/222 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22
摘要： According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal has a frequency different from a clock signal. Therefore, the memory 200 is not required to generate a read data strobe signal from the clock signal nor to send the read data strobe signal in synchronization with the clock signal.
摘要翻译：根据本发明的系统，基于从控制器100发出的数据选通信号，在控制器100和存储器200之间输出/接收数据（DQ）信号。数据选通信号与时钟信号。数据选通信号具有与时钟信号不同的频率。因此，存储器200不需要从时钟信号产生读数据选通信号，也不需要与时钟信号同步地发送读数据选通信号。

3. 发明申请

US20120236666A1 SEMICONDUCTOR MEMORY DEVICE, METHOD OF CONTROLLING READ PREAMBLE SIGNAL THEREOF, AND DATA TRANSMISSION SYSTEM 审中-公开
标题翻译：半导体存储器件，控制其预读信号的方法和数据传输系统
公开(公告)号：US20120236666A1
公开(公告)日：2012-09-20
申请号：US13465826
申请日：2012-05-07
申请人： Atsuo KOSHIZUKA
发明人： Atsuo KOSHIZUKA
IPC分类号： G11C7/22
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C15/00 , G11C15/04
摘要： A system, includes a controller comprising a plurality of first external terminals configured to supply a command and an address, and communicate a data, and communicate a strobe signal related to the data; and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, at least one of the plurality of first external terminals and at least one of the plurality of second external terminals each being capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data between the controller and the semiconductor memory device, the semiconductor memory device further including a preamble resister configured to be capable of storing the information.
摘要翻译：一种系统，包括：控制器，包括被配置为提供命令和地址的多个第一外部终端，并且传送数据，并传送与所述数据相关的选通信号; 以及半导体存储装置，包括对应于多个第一外部端子的多个第二外部端子，所述多个第一外部端子和所述多个第二外部端子中的至少一个能够提供指定的信息所述半导体存储器件在所述半导体存储器件在所述控制器与所述半导体存储器件之间通信数据之前的所述选通信号的前导码的长度，所述半导体存储器件还包括被配置为能够存储所述信息的前同步码抑制器。

4. 发明申请

US20100182856A1 Semiconductor memory device and read wait time adjustment method thereof, memory system, and semiconductor device 有权
标题翻译：半导体存储器件及其读取等待时间调整方法，存储器系统和半导体器件
公开(公告)号：US20100182856A1
公开(公告)日：2010-07-22
申请号：US12656061
申请日：2010-01-14
申请人： Atsuo Koshizuka
发明人： Atsuo Koshizuka
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C8/18 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4096
摘要： A semiconductor memory device operates in synchronization with a system clock, without using a synchronous circuit such as a DLL or a PLL. The semiconductor memory device includes a synchronous circuit for generating output signals phase aligned with the system clock, a synchronous circuit selection circuit that performs switching between a synchronous circuit selection mode and a synchronous circuit non-selection mode, and a reference edge specifying register that specifies an edge of an internal clock which serves as a reference for outputting read data in the synchronous circuit non-selection mode. In the synchronous circuit selection mode, the read data is output by adjusting a phase deviation of the internal clock with respect to the system clock, using the synchronous circuit. In the synchronous circuit non-selection mode, the read data is output in synchronization with the internal clock, without using the synchronous circuit. For a delay of the internal clock with respect to the system clock, the edge of the internal clock used as the reference is adjusted by the reference edge specifying register. Then, even if the synchronous circuit is not used, a large timing deviation does not thereby occur.
摘要翻译：半导体存储器件与系统时钟同步地工作，而不使用诸如DLL或PLL的同步电路。半导体存储装置包括：同步电路，用于产生与系统时钟相位相对的输出信号;执行同步电路选择模式和同步电路非选择模式之间的切换的同步电路选择电路;以及参考边沿指定寄存器，作为在同步电路非选择模式下输出读取数据的基准的内部时钟的边沿。在同步电路选择模式中，使用同步电路，通过调整内部时钟相对于系统时钟的相位偏差来输出读取数据。在同步电路非选择模式下，读取数据与内部时钟同步输出，不使用同步电路。对于相对于系统时钟的内部时钟的延迟，用作参考的内部时钟的边沿由参考边沿指定寄存器调整。然后，即使不使用同步电路，也不会发生大的定时偏差。

5. 发明申请

US20100149889A1 SYSTEM WITH CONTROLLER AND MEMORY 有权
标题翻译：具有控制器和存储器的系统
公开(公告)号：US20100149889A1
公开(公告)日：2010-06-17
申请号：US12710481
申请日：2010-02-23
申请人： Atsuo KOSHIZUKA
发明人： Atsuo KOSHIZUKA
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C7/222 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22
摘要： According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal has a frequency different from a clock signal. Therefore, the memory 200 is not required to generate a read data strobe signal from the clock signal nor to send the read data strobe signal in synchronization with the clock signal.
摘要翻译：根据本发明的系统，基于从控制器100发出的数据选通信号，在控制器100和存储器200之间输出/接收数据（DQ）信号。数据选通信号与时钟信号。数据选通信号具有与时钟信号不同的频率。因此，存储器200不需要从时钟信号产生读数据选通信号，也不需要与时钟信号同步地发送读数据选通信号。

6. 发明授权

US07697369B2 System with controller and memory 有权
标题翻译：带控制器和内存的系统
公开(公告)号：US07697369B2
公开(公告)日：2010-04-13
申请号：US11759862
申请日：2007-06-07
申请人： Atsuo Koshizuka
发明人： Atsuo Koshizuka
IPC分类号： G11C7/00
CPC分类号： G11C7/222 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22
摘要： According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal has a frequency different from a clock signal. Therefore, the memory 200 is not required to generate a read data strobe signal from the clock signal nor to send the read data strobe signal in synchronization with the clock signal.
摘要翻译：根据本发明的系统，基于从控制器100发出的数据选通信号，在控制器100和存储器200之间输出/接收数据（DQ）信号。数据选通信号与时钟信号。数据选通信号具有与时钟信号不同的频率。因此，存储器200不需要从时钟信号产生读数据选通信号，也不需要与时钟信号同步地发送读数据选通信号。

7. 发明授权

US08811052B2 Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system 有权
标题翻译：半导体存储器件，控制其前导码信号的方法和数据传输系统
公开(公告)号：US08811052B2
公开(公告)日：2014-08-19
申请号：US13621061
申请日：2012-09-15
申请人： Atsuo Koshizuka
发明人： Atsuo Koshizuka
IPC分类号： G11C15/00
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C15/00 , G11C15/04
摘要： A system, includes a controller comprising a plurality of first external terminals configured to supply a command and an address, and communicate a data, and communicate a strobe signal related to the data; and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, at least one of the plurality of first external terminals and at least one of the plurality of second external terminals each being capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data between the controller and the semiconductor memory device, the semiconductor memory device further including a preamble register configured to be capable of storing the information.
摘要翻译：一种系统，包括：控制器，包括被配置为提供命令和地址的多个第一外部终端，并且传送数据，并传送与所述数据相关的选通信号; 以及半导体存储装置，包括对应于多个第一外部端子的多个第二外部端子，所述多个第一外部端子和所述多个第二外部端子中的至少一个能够提供指定的信息所述半导体存储器件在所述半导体存储器件在所述控制器与所述半导体存储器件之间通信数据之前的所述选通信号的前导码的长度，所述半导体存储器件还包括被配置为能够存储所述信息的前导码存储器。

8. 发明申请

US20140146623A1 SYSTEM WITH CONTROLLER AND MEMORY 有权
标题翻译：具有控制器和存储器的系统
公开(公告)号：US20140146623A1
公开(公告)日：2014-05-29
申请号：US14170110
申请日：2014-01-31
申请人： Atsuo KOSHIZUKA
发明人： Atsuo KOSHIZUKA
IPC分类号： G11C7/22
CPC分类号： G11C7/222 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22
摘要： According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal has a frequency different from a clock signal. Therefore, the memory 200 is not required to generate a read data strobe signal from the clock signal nor to send the read data strobe signal in synchronization with the clock signal.
摘要翻译：根据本发明的系统，基于从控制器100发出的数据选通信号，在控制器100和存储器200之间输出/接收数据（DQ）信号。数据选通信号与时钟信号。数据选通信号具有与时钟信号不同的频率。因此，存储器200不需要从时钟信号产生读数据选通信号，也不需要与时钟信号同步地发送读数据选通信号。

9. 发明授权

US08614907B2 Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system 有权
公开(公告)号：US08614907B2
公开(公告)日：2013-12-24
申请号：US13620846
申请日：2012-09-15
申请人： Atsuo Koshizuka
发明人： Atsuo Koshizuka
IPC分类号： G11C15/00
摘要： A controller, includes a plurality of external terminals configured to supply a command and an address to a semiconductor memory device, communicate a data with the semiconductor memory device, and communicate a strobe signal related to the data, at least one external terminal among the plurality of external terminals being configured to be capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data.

10. 发明申请

US20130010555A1 SEMICONDUCTOR MEMORY DEVICE, METHOD OF CONTROLLING READ PREAMBLE SIGNAL THEREOF, AND DATA TRANSMISSION SYSTEM 有权
标题翻译：半导体存储器件，控制其预读信号的方法和数据传输系统
公开(公告)号：US20130010555A1
公开(公告)日：2013-01-10
申请号：US13621069
申请日：2012-09-15
申请人： Atsuo KOSHIZUKA
发明人： Atsuo KOSHIZUKA
IPC分类号： G11C7/22
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C15/00 , G11C15/04
摘要： A semiconductor memory device, includes a clock terminal provided to receive a clock signal, a data terminal provided to transfer a data therethrough in synchronization with the clock signal, a strobe terminal provided to be related in the data terminal and to transfer a strobe signal therethrough, a command terminal provided to receive a command that communicates the data with an outside thereof, and an address terminal provided to be supplied an information specifying a length of a preamble of the strobe signal from an outside of the semiconductor memory device, prior to communicating the data.
摘要翻译：一种半导体存储器件，包括：时钟端子，用于接收时钟信号;数据端子，被提供用于与时钟信号同步地传送数据;选通端子，其设置为与数据端子相关并且通过其传送选通信号，提供用于接收与其外部通信数据的命令的命令终端，以及在通信之前提供的来自半导体存储设备的外部的提供指定选通信号的前导码的长度的信息的地址终端数据。

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