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    • 4. 发明授权
    • Thin film transistor and manufacturing method thereof
    • 薄膜晶体管及其制造方法
    • US08598586B2
    • 2013-12-03
    • US12970460
    • 2010-12-16
    • Toshiyuki IsaAtsushi Hirose
    • Toshiyuki IsaAtsushi Hirose
    • H01L29/04
    • H01L29/78696H01L27/12H01L27/124H01L29/04H01L29/66765H01L29/78618H01L29/78648H01L29/78678
    • Disclosed is a thin film transistor including: a gate insulating layer covering a gate electrode; a microcrystalline semiconductor region over the gate insulating layer; a pair of amorphous semiconductor region over the microcrystalline semiconductor; a pair of impurity semiconductor layers over the amorphous semiconductor regions; and wirings over the impurity semiconductor layers. The microcrystalline semiconductor region has a surface having a projection and depression on the gate insulating layer side. The microcrystalline semiconductor region includes a first microcrystalline semiconductor region which is not covered with the amorphous regions and a second microcrystalline semiconductor region which is in contact with the amorphous semiconductor regions. A thickness d1 of the first microcrystalline semiconductor region is smaller than a thickness d2 of the second microcrystalline semiconductor region and d1 is greater than or equal to 30 nm.
    • 公开了一种薄膜晶体管,包括:覆盖栅电极的栅极绝缘层; 栅极绝缘层上的微晶半导体区域; 微晶半导体上的一对非晶半导体区域; 在所述非晶半导体区域上的一对杂质半导体层; 以及杂质半导体层上的布线。 微晶半导体区域具有在栅极绝缘层侧具有突出和凹陷的表面。 微晶半导体区域包括未被无定形区域覆盖的第一微晶半导体区域和与非晶半导体区域接触的第二微晶半导体区域。 第一微晶半导体区域的厚度d1小于第二微晶半导体区域的厚度d2,d1大于或等于30nm。
    • 9. 发明申请
    • THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF
    • 薄膜晶体管及其制造方法
    • US20110147754A1
    • 2011-06-23
    • US12970460
    • 2010-12-16
    • Toshiyuki ISAAtsushi HIROSE
    • Toshiyuki ISAAtsushi HIROSE
    • H01L29/786H01L21/336
    • H01L29/78696H01L27/12H01L27/124H01L29/04H01L29/66765H01L29/78618H01L29/78648H01L29/78678
    • Disclosed is a thin film transistor including: a gate insulating layer covering a gate electrode; a microcrystalline semiconductor region over the gate insulating layer; a pair of amorphous semiconductor region over the microcrystalline semiconductor; a pair of impurity semiconductor layers over the amorphous semiconductor regions; and wirings over the impurity semiconductor layers. The microcrystalline semiconductor region has a surface having a projection and depression on the gate insulating layer side. The microcrystalline semiconductor region includes a first microcrystalline semiconductor region which is not covered with the amorphous regions and a second microcrystalline semiconductor region which is in contact with the amorphous semiconductor regions. A thickness d1 of the first microcrystalline semiconductor region is smaller than a thickness d2 of the second microcrystalline semiconductor region and d1 is greater than or equal to 30 nm.
    • 公开了一种薄膜晶体管,包括:覆盖栅电极的栅极绝缘层; 栅极绝缘层上的微晶半导体区域; 微晶半导体上的一对非晶半导体区域; 在所述非晶半导体区域上的一对杂质半导体层; 以及杂质半导体层上的布线。 微晶半导体区域具有在栅极绝缘层侧具有突出和凹陷的表面。 微晶半导体区域包括未被无定形区域覆盖的第一微晶半导体区域和与非晶半导体区域接触的第二微晶半导体区域。 第一微晶半导体区域的厚度d1小于第二微晶半导体区域的厚度d2,d1大于或等于30nm。