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1. 发明申请

US20100052698A1 Integrated circuit architecture for testing variable delay circuit 失效
标题翻译：用于测试可变延迟电路的集成电路架构
公开(公告)号：US20100052698A1
公开(公告)日：2010-03-04
申请号：US12461853
申请日：2009-08-26
申请人： Tooru Iwashita , Masahiko Shihara , Atsushi Tangoda
发明人： Tooru Iwashita , Masahiko Shihara , Atsushi Tangoda
IPC分类号： G01R27/28
CPC分类号： G01R31/317 , G01R31/31922 , G01R31/31937
摘要： An integrated circuit is provided with first and second variable delay circuits, a test data feeding circuitry, a test control circuit, and a wire-connection line. The test data feeding circuitry feeds first and second test data signals to the first and second variable delay circuits, respectively. The first and second test data signals are complement to each other. The test control circuit feeds first and second drive capability control signals to the first and second variable delay circuits to control drive capabilities of the first and second variable delay circuits. The wire-connection line provides a wire-connection for outputs of the first and second variable delay circuits.
摘要翻译：集成电路设置有第一和第二可变延迟电路，测试数据馈送电路，测试控制电路和有线连接线。测试数据馈送电路将第一和第二测试数据信号分别馈送到第一和第二可变延迟电路。第一和第二测试数据信号彼此互补。测试控制电路将第一和第二驱动能力控制信号馈送到第一和第二可变延迟电路以控制第一和第二可变延迟电路的驱动能力。线连接线为第一和第二可变延迟电路的输出提供有线连接。

2. 发明申请

US20110032014A1 Delay locked loop circuit and signal delay method 审中-公开
标题翻译：延迟锁相环电路和信号延时方式
公开(公告)号：US20110032014A1
公开(公告)日：2011-02-10
申请号：US12801894
申请日：2010-06-30
申请人： Masahiko Shihara , Atsushi Tangoda
发明人： Masahiko Shihara , Atsushi Tangoda
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/0805 , H03L7/0816
摘要： A multiplier PLL multiplies a reference clock and outputs the multiplied clock. A DLL compares the clock output from the multiplier PLL with a clock obtained by delaying the clock output from the multiplier PLL. The DLL generates a delay signal having a given amount of delay based on the comparison result. A delay control signal operation circuit generates a delay control signal based on the delay signal generated by the DLL. A first delay circuit delays an input signal based on the delay control signal generated by the delay control signal operation circuit.
摘要翻译：乘法器PLL将参考时钟相乘并输出相乘的时钟。 DLL将乘法器PLL的时钟输出与通过延迟乘法器PLL的时钟输出获得的时钟进行比较。该DLL根据比较结果产生具有给定量的延迟的延迟信号。延迟控制信号运算电路基于由DLL生成的延迟信号生成延迟控制信号。第一延迟电路基于由延迟控制信号操作电路产生的延迟控制信号延迟输入信号。

3. 发明授权

US07583118B2 Delay locked loop circuit 有权
标题翻译：延时锁定回路电路
公开(公告)号：US07583118B2
公开(公告)日：2009-09-01
申请号：US11588256
申请日：2006-10-27
申请人： Atsushi Hasegawa , Atsushi Tangoda
发明人： Atsushi Hasegawa , Atsushi Tangoda
IPC分类号： H03L7/00
CPC分类号： H03L7/07 , H03L7/0805 , H03L7/0814
摘要： A delay locked loop (DLL) circuit includes a first DLL section configured to receive a reference clock signal, to delay the reference clock signal in response to a first control signal, and to output a phase delayed signal having a predetermined phase delay. A second DLL section delays the reference clock signal in response to a second control signal, and generates the second control signal based on the reference clock signal delayed in the second DLL section and the phase delayed signal. An input signal delay section delays an input signal in response to the second control signal.
摘要翻译：延迟锁定环（DLL）电路包括被配置为接收参考时钟信号的第一DLL部分，以响应于第一控制信号延迟参考时钟信号，并输出具有预定相位延迟的相位延迟信号。第二DLL部分响应于第二控制信号延迟参考时钟信号，并且基于在第二DLL部分中延迟的参考时钟信号和相位延迟信号产生第二控制信号。输入信号延迟部分响应于第二控制信号延迟输入信号。

4. 发明授权

US08395406B2 Integrated circuit architecture for testing variable delay circuit 失效
标题翻译：用于测试可变延迟电路的集成电路架构
公开(公告)号：US08395406B2
公开(公告)日：2013-03-12
申请号：US12461853
申请日：2009-08-26
申请人： Tooru Iwashita , Masahiko Shihara , Atsushi Tangoda
发明人： Tooru Iwashita , Masahiko Shihara , Atsushi Tangoda
IPC分类号： G01R31/26 , G01R31/3187 , H03L7/06
CPC分类号： G01R31/317 , G01R31/31922 , G01R31/31937
摘要： An integrated circuit is provided with first and second variable delay circuits, a test data feeding circuitry, a test control circuit, and a wire-connection line. The test data feeding circuitry feeds first and second test data signals to the first and second variable delay circuits, respectively. The first and second test data signals are complement to each other. The test control circuit feeds first and second drive capability control signals to the first and second variable delay circuits to control drive capabilities of the first and second variable delay circuits. The wire-connection line provides a wire-connection for outputs of the first and second variable delay circuits.
摘要翻译：集成电路设置有第一和第二可变延迟电路，测试数据馈送电路，测试控制电路和有线连接线。测试数据馈送电路将第一和第二测试数据信号分别馈送到第一和第二可变延迟电路。第一和第二测试数据信号彼此互补。测试控制电路将第一和第二驱动能力控制信号馈送到第一和第二可变延迟电路以控制第一和第二可变延迟电路的驱动能力。线连接线为第一和第二可变延迟电路的输出提供有线连接。

5. 发明申请

US20070096784A1 Delay locked loop circuit 有权
标题翻译：延时锁定回路电路
公开(公告)号：US20070096784A1
公开(公告)日：2007-05-03
申请号：US11588256
申请日：2006-10-27
申请人： Atsushi Hasegawa , Atsushi Tangoda
发明人： Atsushi Hasegawa , Atsushi Tangoda
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/0805 , H03L7/0814
摘要： A delay locked loop (DLL) circuit includes a first DLL section configured to receive a reference clock signal, to delay the reference clock signal in response to a first control signal, and to output a phase delayed signal having a predetermined phase delay. A second DLL section delays the reference clock signal in response to a second control signal, and generates the second control signal based on the reference clock signal delayed in the second DLL section and the phase delayed signal. An input signal delay section delays an input signal in response to the second control signal.
摘要翻译：延迟锁定环（DLL）电路包括被配置为接收参考时钟信号的第一DLL部分，以响应于第一控制信号延迟参考时钟信号，并输出具有预定相位延迟的相位延迟信号。第二DLL部分响应于第二控制信号延迟参考时钟信号，并且基于在第二DLL部分中延迟的参考时钟信号和相位延迟信号产生第二控制信号。输入信号延迟部分响应于第二控制信号延迟输入信号。

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